Sr Principal Application Engineer - Design Verification
Cadence Design Systems • Onomichi, Japan
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Role & seniority
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Technical pre-sales / customer-facing solutions role
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Mid-level: ~4–6+ years experience
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Stack / tools
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HDL: Verilog, VHDL (IP/SoC-level design)
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Verification: SystemVerilog/SystemVerilog + HDL simulators
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Formal verification: including Jasper (preferred)
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Emulation/Acceleration: hardware emulator or acceleration platforms
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Methodology: UVM (preferred)
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AI for design/verification (preferred)
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Top 3 responsibilities
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Partner with Sales to scope opportunities for Cadence SoC Verification, AI, Simulation/Emulation/Acceleration solutions
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Plan and execute technical evaluations/benchmarks with customers; compare against existing/alternative solutions
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Train/ramp-up/accompany customer projects; deliver trainings, demos, and technical presentations
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Must-have skills
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Strong Verilog/VHDL SoC/IP design background
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Practical verification experience with SystemVerilog/VHDL and HDL simulators
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Knowledge/experience with formal verification (baseline requirement; Jasper is a plus)
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Japanese: strong verbal and written communication
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Teamwork and ability to work closely with Sales/Engineering
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Nice-to-haves
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Jasper formal verification experience
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Emulator/accelerator experience
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UVM and advanced verification methodology
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AI experience for design and verification
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**Busines
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Full Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Responsibility
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Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, AI solution, simulation Emulation and Acceleration products
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Plan, execute and manage key technical evaluations and benchmark with existing and potential customers
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Train, ramp-up and accompany customer project
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Conduct basic and advanced trainings, presentations and demos as necessary
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Providing technical expertise to address clients’ queries, which need expert involvement
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Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement
. Job Requirement
4-6 or above years’ experience in the following areas
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Design experience in Verilog/VHDL for IP or SoC chip level.
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Verification with knowledge of System Verilog/VHDL and HDL simulators.
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Experience of using formal verification, Jasper experience is a plus.
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Experience with hardware emulator or accelerator is a big advantage.
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Experience of advanced verification methodology like UVM is a plus.
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Experience of AI for design and verification is a big advantage.
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Strong verbal and written communication skills in Japanese is needed.
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Business-level English proficiency is preferred.
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Strong teamwork skills with good human relationship.
