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Mixed Signal Verification Engineer

Prodapt ASIC services (Formerly Innovative Logic) • San Jose, California, United States

onsitecontract
Posted Aug 27, 2026Apply by Sep 26, 2026

**Role & seniority: ** Senior Mixed Signal Verification Engineer (mixed-signal/AMS/DMS verification)

**Location & work type: ** San Jose, CA — 5 days onsite

**Stack/tools: **

  • HDLs: Verilog, SystemVerilog

  • Modeling: RNM (Real/Non-Real) modeling

  • Verification: UVM, digital verification workflows, waveform debug

  • Simulation focus: digital VLSI simulation + mixed-mode/analog simulation (per role needs)

**Top 3 responsibilities: **

  1. Create AMS/DMS testbenches for wireless RF and high-speed PHY

  2. Collaborate with RF/analog design engineers to develop/validate analog circuit models

  3. Support silicon bring-up and commercialization activities

**Must-have skills: **

  • BS/BE minimum; 3+ years relevant experience

  • Strong knowledge of digital VLSI simulation flow

  • Strong knowledge of mixed-mode and analog simulation flow

  • Experience with Verilog/SystemVerilog and RNM modeling

  • Experience with UVM, digital verification, and waveform debugging

  • Team collaboration and strong written/verbal communication

**Nice-to-haves: **

  • Deep understanding of wireless RF transceiver and SerDes PHY technology

Full Description

Prodapt ASIC Services (formerly Innovative Logic) provides end-to-end SoC/ASIC, FPGA, and embedded software solutions. Our design services cover the complete lifecycle from RTL to GDSII, covering domains like 3nm node physical design, UVM verification, DFT, and silicon bring-up for 5G, AI, and IoT.

We are looking for Senior Mixed Signal Verification Engineer in San Jose, CA and its a 5 day onsite position

Job Responsibilities

  • Creating AMS/DMS testbench for wireless RF and High Speed PHY.
  • Working with RF/Analog design engineers for analog circuit models
  • Support silicon bring-up and commercialization.

Required Skills

  • BS or BE minimum, 3+ year experiences
  • Deep understanding of digital VLSI simulation flow
  • Deep understanding of mixed-mode and analog simulation flow
  • Experience with Verilog/SystemVerilog and RNM modeling
  • Experience with digital verification, UVM, and waveform debug
  • Teamwork, dedication, strong communications and interpersonal skills
  • Excellent communication skills both written and verbal PREFERED SKILLS
  • Deep understanding of wireless RF transceiver and Serdes PHY technology

Thanks & Regards Divakar Dhandapani

AMS/DMS TestbenchWireless RFHigh Speed PHYAnalog Circuit ModelsDigital VLSI SimulationMixed-mode SimulationAnalog SimulationVerilogSystemVerilogRNM ModelingUVMWaveform DebugSerdes PHYmulti-location

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