Senior Design Verification Engineer
Oppstar Berhad • Penang, Malaysia
**Role & seniority: ** Functional Verification Engineer (pre-Si verification) — ~4+ years experience (BSEE/MSEE/PhD)
**Stack/tools: **
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Languages: SystemVerilog, UVM
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Verification: UVM/OVM, assertion-based verification, constrained-random verification, reference models, functional coverage
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Tools/flows: Cadence, Mentor Graphics and/or Synopsys
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IP/architecture familiarity: HSST, Ethernet, PCIe, DDR; FPGA and/or ARM
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Top 3 responsibilities:
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Define test plans for IP blocks and full-chip FPGA/ASIC designs
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Develop UVM/SystemVerilog test bench content (stimulus, reference model, assertions, coverage)
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Debug and run regressions to ensure design quality and validation closure
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Must-have skills:
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Strong functional verification experience (planning, TB development, stimulus/reference model, assertions, coverage)
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Proficiency with SystemVerilog + UVM (or OVM), constrained random methodologies
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Ability to debug verification issues and manage regression execution
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Familiarity with common IP protocols and FPGA/ARM architectures
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Hands-on experience with major EDA verification tool flows (Cadence/Mentor/Synopsys)
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Nice-to-haves:
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Deeper domain knowledge in specific protocols (e.g., PCIe/DDR/Ethernet/HSST)
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Prior experience validating complex full-chip integrations and working with DFX/design automation stakeholders
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Location & work type: Not specified in the provided text (cannot infer).
Full Description
Responsibilities
- Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.
- The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.
- Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.
Qualifications
- BSEE/MSEE/PhD with at least 4 years' relevant experience
- Experience in functional verification that may includes test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.
- Experience with modern verification techniques e.g. SystemVerilog OVM/UVM, assertion-based verification, constrained random verification methodologies.
- Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.
- Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.
