
Design Verification Engineer
Apple • Cupertino, California, United States
**Role & seniority: ** Hardware Verification Engineer (3+ years experience; mid-level).
**Location & work type: ** Cupertino, CA (also various unanticipated US locations). Full-time, 40 hours/week.
**Stack/tools (required): **
-
SystemVerilog, constrained-random verification, functional coverage
-
UVM (verification environments; directed + random tests)
-
C/C++ for Verification IP (reference models, checkers)
-
Python/Perl for automation (constraint generation, regression analysis)
-
EDA tools for simulation, debugging, coverage closure
-
High-speed interface protocol verification
-
Digital design understanding (ASIC flows)
-
Computer architecture (memory subsystem/architecture tradeoffs)
**Top 3 responsibilities: **
-
Review SoC/IP/subsystem specs; develop and maintain test/coverage plans.
-
Build and run simulation-based verification using SystemVerilog + UVM; develop Verification IP (models/checkers).
-
Debug simulation failures (waveforms/logs/signals) and drive coverage/milestone tracking via internal tools.
**Must-have skills: **
-
SystemVerilog constrained-random + functional coverage
-
UVM testbench development and test creation
-
C/C++ verification IP development
-
Python/Perl automation for regression and constraint generation
-
EDA simulation/debug; achieving coverage closure
-
Ability to verify high-bandwidth, low-power data communication interfaces
**Nice-to-haves: **
- None liste
Full Description
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
DESCRIPTION
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Review SoC/IP/Subsystem specifications for system-on-chip(S0C), IP blocks, and subsystems to understand design requirements and expected functionality. Develop and maintain comprehensive test plans and coverage plans to ensure complete verification of hardware components. Write and execute simulation-based verification tests using hardware description and verification languages such as System Verilog. Collaborate closely with design and micro-architecture teams to clarify functionality, review new features, and align on test coverage goals. Debug simulation failures by analyzing waveforms, error logs, and internal signals to identify the root cause and assist in resolution. Track verification progress using internal project management tools, ensure all milestones are met, and test coverage metrics are updated regularly. Participate in recurring meetings and technical reviews to communicate progress, discuss challenges, and aligning tasks with team priorities Document test methodologies, debugging procedures, and verifying results to contribute to team knowledge and supporting ongoing development. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $155,896 - $225,300/yr and your base pay will
depend on your skills, qualifications, experience, and location. PAY & BENEFITS
- Apple employees also have the opportunity to become an Apple shareholder through
- participation in Apple’s discretionary employee stock programs. Apple employees
- are eligible for discretionary restricted stock unit awards, and can purchase
- Apple stock at a discount if voluntarily participating in Apple’s Employee Stock
Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or
commission payments as well as relocation. Learn more about Apple Benefits
https: //www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
MINIMUM QUALIFICATIONS
Bachelor’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field and 3 years of experience in the job offered or
related occupation. 3 years of experience in the following skills are required
- Utilizing System Verilog for constrained random verification and functional
- coverage. Utilizing UVM to develop verification environments and implement
- directed and random test cases. Utilizing C and C++ to develop Verification IP
- including reference models and checkers. Utilizing Python and Perl for creating
- automation tools, constraint generation, and regression analysis. Utilizing EDA
- tools for testbench simulations, debugging, and coverage closure. Utilizing
- High-speed interface protocols for verifying high bandwidth, low power data
communication systems. Education and/or experience must include: Utilizing Digital Design for understanding ASIC design flows and verification. Utilizing Computer Architecture for exploration of memory subsystem and architecture trade-off analysis.
PREFERRED QUALIFICATIONS
N/A