**Role & seniority: ** SoC Verification Engineer (6–12 years) for hands-on Ethernet/SerDes verification; owns verification from UVM env to compliance testing and signoff.

**Location & work type: ** Bengaluru (work type not specified; assumed on-site/hybrid not stated).

**Stack/tools: ** SystemVerilog, UVM, constrained-random verification, assertions (SVA), functional coverage; verification automation with Python/C/C++; simulation/waveform debug.

**Top 3 responsibilities: **

Build and execute verification strategies for Ethernet-based SoC subsystems (functional + corner cases).
Develop/maintain SystemVerilog/UVM verification environments: agents, sequences, monitors, checkers, scoreboards, coverage models.
Perform Ethernet protocol/compliance/interoperability testing for SerDes + controllers (MAC/PCS/PHY interfaces) and debug issues; drive coverage closure and signoff.
Must-have skills:
- 6–12 years SoC/IP verification experience.
- Strong hands-on SystemVerilog + UVM development.
- Deep Ethernet protocol knowledge and compliance validation; familiarity with MAC/PCS and PHY/high-speed interfaces.
- Constrained-random, assertions, functional coverage; strong RTL/system-level debug skills.
- Ability to verify SerDes, Ethernet controllers, and related interfaces.
Nice-to-haves:
- Python/C/C++ for verification automation.
- Experience with interoperability/compliance test execution across multi

Full Description

SoC Verification Engineer

Location: Bengaluru

Experience: 6–12 Years Role Overview We are looking for an experienced SoC Verification Engineer with strong expertise in Ethernet protocol verification, compliance validation, SerDes/controller verification, and UVM environment development. Key Responsibilities Develop and execute verification strategies for Ethernet-based SoC subsystems. Drive Ethernet protocol and compliance verification across functional and corner-case scenarios. Develop, enhance, and maintain SystemVerilog/UVM verification environments. Verify SerDes, Ethernet controllers, MAC/PCS and related interfaces. Develop UVM agents, sequences, scoreboards, monitors, checkers and coverage models. Perform protocol, interoperability and compliance testing and debug failures at RTL/system level. Drive coverage closure, regression, debug and verification signoff. Collaborate with RTL, architecture, firmware and validation teams to resolve complex issues. Core Technical Skills 6–12 years of SoC/IP Design Verification experience. Strong hands-on expertise in SystemVerilog & UVM. Deep understanding of Ethernet protocols and compliance verification. Experience with SerDes/controller validation. Strong knowledge of MAC/PCS, Ethernet PHY interfaces and high-speed protocols. Experience with constrained-random verification, assertions and functional coverage. Strong debugging skills using simulation/waveform analysis. Python/C/C++ scripting for verification automation is a plus.

Ideal Profile: A hands-on verification engineer capable of owning Ethernet/SerDes verification from UVM environment development through compliance testing, coverage closure and signoff.