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Hiring For Design Verification Engineer

Techmahindra Bengaluru, Karnataka, India

onsitefull-time
Posted Sep 11, 2026Apply by Oct 11, 2026

Hi Everyone

We are hiring For Design Verification and GLS Engineer

Exp: 4 to 12 Years

Np: Immediate to 30 days

Key skills: UVM, SV, Verilog, High speed protocols and Power Management (Plus advantage)

Key Responsibilities Develop directed and constrained-random testcases De

Full Description

Hi Everyone

We are hiring For Design Verification and GLS Engineer

Exp: 4 to 12 Years

Np: Immediate to 30 days

Key skills: UVM, SV, Verilog, High speed protocols and Power Management (Plus advantage)

Key Responsibilities Develop directed and constrained-random testcases Debug failures and root-cause issues across RTL, testbench, and tools RTL as well as Gate level simulations Automate regression flows and improve verification productivity Required Skills & Qualifications Technical Skills Good knowledge of SystemVerilog Hands-on experience with UVM (Universal Verification Methodology) Experience with EDA tools (e.g., VCS, Verdi) Experience in debugging RTL and gate level simulation issues Good knowledge of PCIe protocol Programming/Scripting Proficiency in Python/Perl/Shell scripting for automation

UVMSystemVerilogVerilogHigh speed protocolsPower ManagementRTLGate level simulationsVCSVerdiPCIePythonPerlShell scriptingRegression flowsDebuggingmulti-location

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