**Role & seniority: ** Senior Staff Engineer – IP/SoC Verification (12–16 years)

**Stack/tools: **

HDL/verification: SystemVerilog, UVM, SVA (assertions)
Verification methods: constrained-random, functional coverage, reference models
Protocols (verification): PCIe, CXL, Ethernet, DDR, USB
Automation/scripting: Python, Perl, or Tcl
Debug: simulation + waveform analysis; regression infrastructure (tools not specified)
Collaboration: RTL Design/Architecture, Emulation, Firmware, Post-Silicon
Top 3 responsibilities:
- Own and execute IP/SoC verification strategy, planning, execution, and signoff
- Architect and build scalable UVM/SystemVerilog testbenches (agents/drivers/monitors/scoreboards/reference models)
- Lead block/subsystem/SoC-level functional verification including integration, end-to-end validation, coverage closure, and regression management
Must-have skills:
- Deep SystemVerilog + UVM expertise
- Proven testbench architecture experience (including building from scratch)
- Strong high-speed protocol verification knowledge
- Solid coverage closure capability (functional coverage + constrained-random) and SVA assertions
- Effective debugging of complex RTL/protocol/system issues
- Ability to work across teams and drive mentorship/methodology improvements
Nice-to-haves:
- Specific protocol exposure: **PCIe Gen4/5/6, CXL, DDR4/DDR5, LPDDR, Ethern

Full Description

Senior Staff Engineer – IP/SoC Verification Role Overview We are looking for a Senior Staff Engineer – IP/SoC Verification with deep expertise in SystemVerilog, UVM, testbench architecture, and high-speed protocol verification. The ideal candidate will drive verification strategy, develop scalable verification environments, and lead functional verification of complex IPs and SoCs. Key Responsibilities Own IP/SoC verification strategy, planning, execution, and signoff. Architect and develop scalable SystemVerilog/UVM testbenches. Drive testbench development, including UVM agents, drivers, monitors, scoreboards, and reference models. Verify high-speed protocols such as PCIe, CXL, Ethernet, DDR, and USB. Develop comprehensive test plans, functional coverage, assertions, and constrained-random tests. Lead block, subsystem, and SoC-level verification, including integration and end-to-end validation. Debug complex RTL, protocol, and system-level issues using simulation and waveform analysis. Drive coverage closure, regression management, and verification signoff. Collaborate with RTL Design, Architecture, Emulation, Firmware, and Post-Silicon teams. Mentor engineers and contribute to verification methodology and automation improvements. Core Technical Skills 12–16 years of hands-on IP/SoC Design Verification experience. Strong expertise in SystemVerilog and UVM. Proven experience in testbench architecture and development from scratch. Deep understanding of high-speed protocols and interface verification. Strong knowledge of functional coverage, assertions (SVA), constrained-random verification, and coverage closure. Experience with UVM methodology, reusable verification components, and regression infrastructure. Strong debugging skills in complex IP and SoC environments. Proficiency in scripting languages such as Python, Perl, or Tcl. Preferred Qualifications Experience with PCIe Gen4/5/6, CXL, DDR4/DDR5, LPDDR, Ethernet, or USB. Exposure to SoC integration, coherency, memory subsystems, or high-performance compute designs. Experience with formal verification, emulation, or hardware acceleration. Strong technical leadership, architectural ownership, and cross-functional collaboration. Education

B. E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.