Low Power Verification Engineer, Physical Design
Google • Sunnyvale, California, United States
**Role & seniority: ** Senior ASIC post-layout physical netlist validation / low-power signoff engineer (≈ 8+ years experience)
**Stack / tools: **
-
Low-power rule-checking: VCLP / CLP (e.g., Synopsys VCLP)
-
Physical design/P&R context: Innovus, Fusion; CTS (Clock Tree Synthesis) debugging
-
Low-power frameworks/flows: UPF (IEEE 1801), UPF scripts, PST (Power State Tables)
-
ECO automation: Tcl/Python (preferred)
-
Top 3 responsibilities:
-
Design & execute post-layout low-power verification to meet tapeout signoff (multi-voltage implementation)
-
Validate multi-voltage / UPF collateral at gate level, including power/ground integrity and UPF alignment; debug structural checks and corruption issues
-
Resolve complex P&R/physical anomalies (e.g., wrong-domain buffering, secondary power routing failures, isolation clamp errors) and debug CTS interactions (level shifters, skew/duty-cycle issues)
-
-
Must-have skills:
-
Post-layout physical netlist validation and low-power signoff in advanced ASIC workflows
-
Proficiency with static low-power rule-checking tools (VCLP/CLP), including debugging check failures
-
Experience validating special low-power components: isolation cells, power switches, level shifters, retention regs, always-on cells across synthesis → P&R
-
Strong understanding of multi-voltage and UPF-based flows
-
-
Nice-to-haves:
- MS/PhD (
Full Description
MINIMUM QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 8 years of experience performing post-layout physical netlist validation and low-power signoff within advanced ASIC design workflows.
- Experience with static low-power rule-checking tools (such as VCLP or CLP), including experience in debugging structural checks and signal corruption issues.
- Experience validating special low-power components (isolation cells, power switches, level shifters, retention registers, and always-on cells) across all stages from synthesis to place and route.
PREFERRED QUALIFICATIONS
-
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
-
Experience with scripting languages (e.g., Tcl or Python) to automate Engineering Change Orders (ECOs) and improve verification workflows.
-
Experience interacting with P&R tools (Innovus, Fusion) and an understanding of standard cell timing, hierarchical construction, and physical logic optimization.
-
Experience with UPF implementation, low-power architecture design, and resolving low-power check violations.
-
Expertise in resolving technical issues within the IEEE 1801 UPF framework and physical gate-level netlist flow.
-
Familiarity with timing-driven Place and Route, including insertion, scaling, level shifters, and always-on cells.
ABOUT THE JOB
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google
[https: //www.google.com/about/careers/applications/benefits/].
RESPONSIBILITIES
- Design, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tapeout signoff criteria to ensure successful multi-voltage implementation.
- Validate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools (e.g., Synopsys VCLP) to ensure power/ground integrity and Unified Power Format (UPF) alignment.
- Drive the resolution of complex Physical Design and Place & Route (P&R) anomalies, specifically mitigating issues such as wrong domain buffering, secondary power routing failures, and isolation clamping errors.
- Perform debugging on advanced Clock Tree Synthesis (CTS) implementations, analyzing tool behavior around level shifters in high fanout networks, duty cycle distortions, and multi-voltage skew management.
- Drive the continuous refinement of power state tables (PST) and Unified Power Format (UPF) scripts to ensure accurate translation from Golden RTL to the final physical netlist.
