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Hardware Verification Engineer

Arteris • Krakow, Lesser Poland Voivodeship, Poland

onsitefull-time
Posted Sep 25, 2026Apply by Oct 25, 2026

**Role & seniority: ** Hardware Verification Engineer (≥2 years industry experience)

**Location & work type: ** Krakow, Poland (work arrangement not specified)

**Stack/tools (explicit): **

  • Languages: Verilog, SystemVerilog, VHDL, SystemC, Python, C++ (plus Shell scripting)

  • Verification methods/infrastructure: UVM, VIPs, testbeds, BFMs/monitors, EDA simulators (Cadence, Synopsys)

  • Formal verification: Formal proof (plus)

  • Protocols: AMBA, OCP, others (communication protocols)

**Top 3 responsibilities: **

  • Define/document/develop/execute RTL verification tests and coverage for parameterized SoC/chiplet IP using Python/C++; run on major RTL simulators.

  • Maintain and improve verification workflows, metrics, and automation.

  • Build verification components (BFMs, monitors) for RTL test benches; contribute to robust verification of interconnect/IP.

**Must-have skills: **

  • ≥2 years verification engineering experience

  • Strong RTL verification + RTL/verification language knowledge (listed above)

  • Experience with verification infrastructure (VIPs/UVM/testbeds/EDA tools)

  • Shell scripting experience

  • Understanding of hardware communication protocols (AMBA/OCP/etc.)

  • Team collaboration; quality-focused, results-oriented; fluent English

**Nice-to-haves: **

  • Formal proof verification methodology experience

  • Interconnect technology knowledge

  • Polish and/or French

**Education: ** Master’s or Doct

Full Description

Location: Krakow

Arteris connects innovation.

Our technology helps the world’s most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive, to the AI in the cloud, Arteris connects the innovative tech that shapes tomorrow.

What You’ll Do as a Hardware Verification Engineer at Arteris

Join our innovative team and help shape the future of semiconductor technology, specifically system-on-chip (SoC) and chiplets. In this role, you will contribute to design, implement, and execute robust verification strategies to ensure the correctness, performance, and reliability of complex hardware IP and interconnect solutions., collaborating with cross-functional teams to drive impact across cutting-edge products and solutions.

Key Responsibilities

Define, document, develop and execute RTL verification test/coverage for extremely parameterized IPs in Python and C++, capable of running on any available RTL simulator (Cadence, Synopsys, etc.). Maintain and improve verification workflows. Improve metrics and increase automation. Implement verification components such as BFMs or monitors used in verification test benches.

What You Bring

At least 2 years of industry experience as a verification engineer. Understanding of hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, SystemVerilog). Strong experience in the use and development of verification methods and infrastructure (VIPs, UVM, testbeds, EDA tools). Experience in formal proof verification methodology is a plus Shell scripting experience Understanding of hardware communication protocols (AMBA, OCP, others) Curious, autonomous, rigorous and results-oriented, with a commitment to quality and a thorough approach to work. Proven ability to work well in a team environment Fluent English is a must.

Bonus Points If You Have

Knowledge of interconnect technology is a plus Knowledge of Polish and/or French

Education Requirements

Master’s degree or Doctorate in engineering or computer science

About Arteris

Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster. Learn more at arteris.com.

With over 350 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.

RTL VerificationPythonC++VHDLVerilogSystemCSystemVerilogUVMVerification IPTestbench DevelopmentEDA ToolsFormal VerificationShell ScriptingAMBAOCPHardware Communication Protocolsmulti-location

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