SoC Verification Engineer | UVM & System Verilog Specialist
Texas Instruments • Bengaluru, Karnataka, India
**Role & seniority: ** Digital Verification Engineer — 3–5 years experience (IP/Subsystem/SoC DV ownership through post-silicon)
**Stack/tools: ** C-based SOC DV; SystemVerilog UVM; Verilog/VHDL debugging; Python/Perl/Shell scripting; DV flows for functional/Formal; Cadence (e.g., Xcelium, vManager, Formal, safety simulator) or similar; Formal verification; ISO 26262-aligned safety/signonoff; supports GLS/PAGLS, CPF/UPF and AMS-related verification; post-silicon verification
**Top 3 responsibilities: **
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Own verification end-to-end: spec definition → verification strategy/plan → RTL/PARTL verification → post-silicon verification and customer issue support
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Define DV strategy: 100% spec-to-regression traceability and signoff metrics; create checkers/coverage monitors; update DV flow as needed
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Drive cross-functional collaboration (Architecture, RTL, PD, DFT, Systems, Analog, FW, application) to meet verification goals and deliver SoC DV signoff
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Must-have skills:
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UVM/SystemVerilog depth; C-based SOC DV environment experience
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Strong digital fundamentals (computer architecture, bus protocols) + debugging skills with Verilog/VHDL
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Protocol knowledge (e.g., AXI/AHB/APB/CAN/Ethernet/I2C/SPI/UART/PSI5/FlexRay)
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DV flow ownership (functional/Formal) and regression/coverage/traceability for signoff (ISO 26262)
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Nice-to-haves:
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AMS/GLS/PAGLS/CPF/UPF-based verification experience
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ARM/DSP multi-processor syste
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Full Description
Responsibilities
Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes
Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.
DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines
Qualifications
- 3- 5 of DV experience in SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations
Skills
Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc. Strong in digital design fundamentals, computer organization & architectures and bus protocols Excellent debugging skills with Verilog/VHDL designs
Thorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etc Work experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plus Good problem-solving skills Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Exposure to CDC DV, Post silicon verification and functional safety is an added advantage Effective communication skills to interact seamlessly with all stakeholders Must be highly focused and remain committed to obtaining closure on project goals
