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Staff Design Verification Engineer

onsemi • Bengaluru, Karnataka, India

onsitefull-time
Posted Sep 29, 2026

**Role & seniority: ** Staff ASIC/SoC Verification Engineer (senior; ~10+ years)

**Stack/tools: **

  • HDL/Verification: SystemVerilog, UVM/OVM, assertions, directed/random stimulus, code/functional coverage

  • Languages/Automation: C/C++, Python, Perl, Tcl, Verilog PLI, shell, Make

  • Protocols/Interfaces: ARM-based SoC, AMBA AXI/AHB/APB, familiarity with I2C/SPI

  • Verification topics: constraint-random verification, coverage closure, debug; formal verification (advantage)

  • Power: UPF/CPF (plus)

  • Other: GLS, timing verification

  • AI/ML in verification: intelligent stimulus/failure triage/coverage optimization (exposure)

  • Top 3 responsibilities:

    • Develop and execute verification plans, achieve coverage closure and functional correctness/robustness

    • Build/extend UVM/OVM testbenches and reusable VIP, coordinate with third-party VIP

    • Apply ASIC verification methodology: constraint-random, assertions/coverage, integrate automation for metrics/debug

  • Must-have skills:

    • Strong SystemVerilog + UVM/OVM, advanced verification methodologies

    • SoC/IP verification experience (10+ yrs) with ARM/AMBA (AXI/AHB/APB) and system interactions

    • Scalable, reusable testbench architecture; coverage-driven verification and metrics

    • Debugging/problem-solving and effective communication

    • Scripting/automation capability (Python/Perl/Shell

Full Description

We are seeking an experienced Staff ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit.

#LI-RT1

RESPONSIBILITIES

Responsibilities

  1. Verification Planning and Execution:

      • Develop and execute comprehensive verification plans.
      • Close verification with coverage closure, ensuring high-quality results.
      • Apply standard ASIC verification techniques, including test planning,
      • testbench creation, code and functional coverage, directed and random
      • stimulus generation, and assertions.
  2. Testbench Development:

      • Create and enhance testbenches using SystemVerilog (OVM/UVM) or other
      • standard testbench languages.
      • Implement reusable Verification IP (VIP) components.
      • Collaborate with third-party VIP providers.
  3. Methodology and Flows:

      • Demonstrate a solid understanding of ASIC design and verification
      • methodologies.
      • Apply object-oriented programming principles effectively.
      • Implement constraint random verification methodology.
  4. Technical Skills:

      • Proficiency in SystemVerilog (OVM/UVM) and other relevant languages
      • (C/C++, Perl, Tcl, Python, Verilog PLI).
      • Familiarity with industry standards (e.g., I2C/SPI).
      • Experience with low-power verification using UPF (Unified Power Format) is
      • a plus.
      • Knowledge of formal verification techniques is advantageous.
  5. Collaboration and Communication:

      • Work effectively with internal teams and external customers.
      • Strong written and verbal communication skills.
      • Initiative, analytical problem-solving abilities, and adaptability within
      • a diverse team environment.

QUALIFICATIONS

Required Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 10 Years of experience in SoC/IP verification,.
  • Strong expertise in SystemVerilog, UVM, and advanced verification methodologies.
  • Hands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.
  • Proven ability to build reusable, scalable testbench architectures.
  • Solid understanding of test planning, coverage-driven verification, and verification metrics.
  • Experience with GLS, timing verification, and debug.
  • Knowledge of power-aware verification (UPF/CPF).
  • Strong scripting and automation skills (Python, Perl, Shell, Make, etc.).
  • Exposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).
  • Excellent problem-solving, debugging, and communication skills.
  • #LI-RT1

onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here

https: //www.onsemi.com/careers/career-benefits

[https: //www.onsemi.com/careers/career-benefits]

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

SystemVerilogUVMASIC verificationSoC verificationARM-based SoCAMBA protocolsPythonPerlUPFFormal verificationConstraint random verificationTestbench developmentCoverage-driven verificationGLSTiming verificationDebuggingmulti-location

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