Senior Design Verification Engineer
Sequans Communications • Ramat Gan, Tel-Aviv District, Israel
**Role & seniority: ** Design Verification Engineer (senior; 15+ years ASIC verification)
**Stack/tools: **
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UVM / SystemVerilog (UVM methodology, constrained-random verification, ABV)
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EDA simulators: Questa, Xcelium
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Verification techniques: SVA (assertion-based), CDV (functional-driven verification), formal property checking
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Reference models: C++ (bit-accurate golden models)
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Automation/CI: Python, Git, GitLab CI, scripting; build/automation (SCons, Makefile); regression management & data parsing
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Top 3 responsibilities:
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Architect, build, optimize, and maintain scalable reusable UVM verification environments
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Integrate C++ reference models and implement verification flows (UVM + ABV/CDV + formal)
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Create automation/tools and manage regressions/CI to drive verification closure and sign-off metrics
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Must-have skills:
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Deep hands-on ASIC/SOC verification using UVM + SystemVerilog
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Proficiency in constrained-random and assertion-based verification (SVA/ABV)
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Experience with Questa/Xcelium and unit-to-subsystem/full-chip verification
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Strong Python + Git + GitLab CI for regression and flow automation; scripting for data parsing
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Nice-to-haves:
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C/C++ knowledge beyond reference models
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System-level understanding; SOC communications experience as an advantage
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Location & work type: Not specified in the provided text
Full Description
The Design Verification Engineer is responsible for architecting, deploying, and maintaining advanced pre-silicon test benches, reference models, and automated verification flows to achieve sign-off quality using UVM methodology.
In this role, you will build the UVM verification infrastructure and work closely with chip architects, RTL/VLSI design, Design, and Platform Integration (PI) teams within an advanced development environment, leveraging state-of-the-art development and verification tools to identify, debug, and support the resolution of complex hardware anomalies.
RESPONSIBILITIES As a Design Verification Engineer, you will be responsible for different HW blocks at module-level and sub-system level. You will contribute across a range of technical areas, playing a key role in ensuring high-quality, scalable, and efficient verification solutions.
UVM environment architecture: Design build, Optimize and maintain scalable and reusable UVM environment.
Reference model integration: Integrate and support high level bit accurate reference models in C++ to serve as golden reference in UVM environment.
Modern verification techniques: Deploy advanced methodologies including Assertion-based verification (SVA), Functional driven verification (CDV), and formal property checking to maximize efficiency.
Automation & Tool creation: Develop internal tools, advanced scripting infrastructure and continuous integration (CI/CD), regressions flows (Gitlab CI). Driving the team’s verification efforts.
Methodology & Sign-off: Review verification plans and establish infrastructure metrics (functional coverage, code coverage and formal proofs) to drive verification closure.
REQUIRED EXPERIENCE & KNOWLEDGE Engineering degree with 15+ years of hands-on experience in ASIC verification using UVM System Verilog Experience on methodologies such as UVM, constrained-Random Verification and Assertion Based Verification (ABV).
Experience in using modern EDA Tools Suites: Front-end IC simulation and verification tools (Questa, Xcelium). Experience in unit-level as well as subsystem/full-chip verification. Experience working on complex ASIC or SOC designs Experience in Infrastructure Automation with strong proficiency in Python, SCons, MakeFile, git for automated flow generation, regression management and data parsing. Good knowledge of C/C++ is a plus System-Level understanding Experience with SOCs in the communications field – advantage
