**Role & seniority: ** ASIC Verification Engineer (functional verification) — 5–7 years experience

**Stack/tools: **

Languages: C/C++, C++ (OOP, STL), Linux
HW/verification: Verilog/SystemVerilog (preferred), SystemC (preferred)
Verification methods: directed + constrained-random testing, assertions (ABV) preferred, hardware modeling preferred
Interfaces: DPI/PLI (preferred) in C/Verilog environment
Build/scripting: Perl, Makefiles
Debug: GDB, Valgrind
Top 3 responsibilities:
- Develop and execute test plans (directed and constrained-random) for complex ASIC/IP blocks in simulation
- Perform functional verification as part of a design+verification team, validating functionality within block/chip/system context
- Document verification results and adopt evolving verification methodologies within active SoC projects
Must-have skills:
- Strong C/C++ skills on Linux; OOP, STL, data structures; computer architecture understanding
- Practical debug ability with GDB/Valgrind
- Ability to write/execute SystemVerilog/Verilog-based verification and understand simulation infrastructure
- Strong analytical skills and written communication
Nice-to-haves:
- SystemVerilog/SystemC experience beyond baseline; assertion-based verification familiarity
- Experience with DPI/PLI integrations (C/Verilog)
- Knowledge of hardwa

Full Description

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.

5-7 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting
Strong background in C/C++ development in a Linux Environment
Strong debug skills and experience with debug tools such as Gdb, Valgrind
Proficient in Object Oriented programming, STL, computer architecture and data structures
Knowledge of Perl and Makefiles
Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred
Strong analytical skills and attention to detail
Excellent written and communication skills