**Role & seniority: ** Design Verification CAD Engineer (DV/Verification Infrastructure), 8–12 years

**Location & work type: ** Bengaluru (work type not specified; assumed onsite/hybrid per typical DV CAD roles)

**Stack/tools: **

Languages: Python, Perl, Bash
Verification: SystemVerilog, UVM
Simulation tools: VCS, Xcelium, Questa
OS/infra: Linux/Unix, Git
Processes: CI/CD pipelines, automated regression, coverage/reporting flows, dashboards

**Top 3 responsibilities: **

Own DV infrastructure and regression management for large ASIC/SoC programs.
Develop/maintain scalable simulation + regression + coverage + reporting flows.
Build automation and CI/CD pipelines integrating compilation, simulation, regression, and coverage; improve debug/triage efficiency.

**Must-have skills: **

8–12 years experience in DV CAD / Verification Infrastructure
Strong regression management and DV infrastructure experience
Strong scripting in Python/Perl/Bash
Hands-on CI/CD and automation framework development
Solid SystemVerilog/UVM knowledge
Experience with VCS/Xcelium/Questa
Linux/Unix, Git, automation workflow familiarity
Debugging/problem-solving and cross-team collaboration

**Nice-to-haves: **

Not explicitly listed; could include stronger experience across multiple tools/systems and demonstrated methodology standardization across projects.

Full Description

Design Verification CAD Engineer

Location: Bengaluru

Experience: 8–12 Years Role Overview We are looking for a Design Verification CAD Engineer to build and optimize verification infrastructure, regression frameworks and automation for large-scale ASIC/SoC programs. Key Responsibilities Own DV infrastructure and regression management for complex SoC/IP verification environments. Develop and maintain scalable simulation, regression, coverage and reporting flows. Build automation frameworks using Python, Perl and Bash. Develop and maintain CI/CD pipelines for verification flows and automated regression. Integrate simulation, compilation, regression and coverage tools into automated workflows. Monitor regression health, analyze failures and improve debug and triage efficiency. Develop dashboards, reports and automation for regression status, coverage and verification metrics. Optimize regression infrastructure for scalability, performance and resource utilization. Collaborate with Design Verification, RTL, CAD and Infrastructure teams to resolve flow and infrastructure issues. Drive methodology improvements and standardization across verification projects. Required Skills 8–12 years of experience in DV CAD / Verification Infrastructure. Strong experience in DV infrastructure and regression management. Strong scripting/programming skills in Python, Perl and Bash. Hands-on experience developing CI/CD flows and automation frameworks. Strong understanding of SystemVerilog/UVM-based verification environments. Experience with simulation tools such as VCS, Xcelium or Questa. Good understanding of Linux/Unix environments, Git and automation workflows. Strong debugging, problem-solving and cross-functional collaboration skills.