Role & seniority
- Design Verification Engineer (DV)
- Mid–Senior (requires 8–10+ years hands-on verification experience)
Stack/tools
- Languages/verification: SystemVerilog, UVM (also OVM), C/C++
- Verification methods: IP/sub-system and SoC verification, UVM environment from scratch
- Protocols: AMBA, PCIe, DDR, USB, Ethernet
- CPU targets: ARM/RISC-V CPU sub-systems/SoCs
- E-tools & scripting: Python, TCL, Perl, Shell
- Revision control: Git, SVN, Mercurial (Hg)
Top 3 responsibilities
- Define/implement IP/SoC verification plans and build verification testbenches
- Develop functional tests and execute verification to meet metrics (test plan, functional, code coverage)
- Debug/root-cause functional failures with the design team and drive issues to resolution
Must-have skills
- 8/10+ hands-on SystemVerilog + UVM/OVM verification
- 8/10+ IP/sub-system and/or SoC-level verification experience
- Ability to architect/implement UVM verification infrastructure and run full verification cycle
- Strong debugging/root-cause skills for functional failures
Nice-to-haves
- Experience across multiple protocol domains (AMBA/PCIe/DDR/USB/Ethernet)
- Verification experience specifically targeting ARM or RISC-V CPU sub-systems/SoCs
- Tool/flow development using scripting (Python/TCL/Perl/Shell) and E-tools expert

Full Description

L&T Technology is looking to hire for Design Verification Engineers.

Job Location: Bangalore

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
Experience in development of UVM based verification environments from scratch
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team