Role & seniority
- CPU core verification (digital verification engineer)
- 6+ years experience; open to multiple seniorities (level determined in interviews)
- Ownership of CPU core-level verification for out-of-order RISC-V behavior
Stack/tools
- RTL verification (waveforms, logs, complex debug)
- UVM testbench development
- Assembly and C/C++ stimulus
- Emulation + post-silicon style regression/debug workflows
- RISC-V ISA/extension verification; un-core components coverage
Top 3 responsibilities
- Plan and drive functional verification for CPU core features and microarchitectural scenarios
- Build/extend UVM testbenches, functional models, and coverage for ISA, RISC-V extensions, and un-core
- Debug regressions (sim/emulation), identify root causes using RTL understanding, waveforms, and logs; improve coverage closure
Must-have skills
- 6+ years in CPU verification or closely related DV/digital design
- Strong depth in high-performance out-of-order CPU microarchitecture
- Proficiency working with RTL, UVM, assembly/C/C++ stimulus, and debug artifacts (waveforms/logs)
- Cross-team communication (design, DV, emulation, post-silicon)
Nice-to-haves
- Experience spanning pre-silicon + emulation + post-silicon with shared stimulus
- Building verification infrastructure to scale coverage/debug across multiple CPU programs
- Familiarity with broader

Full Description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are You bring 6+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams.

What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and test teams to support bring-up and delivery of robust CPU cores and clusters.

What You Will Learn How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters. Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus. Ways to scale coverage, debug, and infrastructure across multiple CPU programs. How open hardware and software fit into Tenstorrent’s broader compute roadmap.

Sr Engineer/Staff Engineer, CPU Core Verification

Full Description