Role & seniority
- Physical Verification (PV) Design Engineer (VLSI), responsible for block-level and full-chip PV signoff; likely mid-to-senior (mentions mentoring/junior reviews)
Stack/tools

Industry-standard PV/verification tool flow for

- **DRC/LVS/ERC**, antenna/density/reliability checks

Runsets/decks/automation flows (tool-specific; not named)
Interfaces with PDK/CAD and foundry/EDA vendors
Top 3 responsibilities
- Own block + full-chip PV signoff ensuring foundry + reliability compliance
- Drive signoff closure: identify, debug, and resolve PV violations with PD/layout teams
- Maintain/upgrade verification flows: develop runsets/decks, analyze foundry deck/PDK updates, manage regressions/hierarchical verification
Must-have skills
- Strong PV fundamentals and practical execution of DRC, LVS, ERC
- Expertise in antenna, density, EM/IR, latch-up, ESD-related reliability checks
- Ability to correlate PV findings to layout/PD root causes (spacing/density/routing hotspots)
- Proficiency in automation/flow setup (runsets/decks), and regression/hierarchical verification management
- Cross-functional collaboration (PD, PDK, CAD, tapeout) and participation in tapeout readiness reviews
Nice-to-haves

PV exposure to/understanding of PD concepts

- Floorplanning, congestion, **macro placement**

- **PDN design** considerations (IR drop)

- Placement/CTS

Full Description

We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.

Key Responsibilities

Perform physical verification (PV) for block-level and full-chip designs, including

Design Rule Check (DRC)
Layout Versus Schematic (LVS)
Electrical Rule Check (ERC)
Antenna, density, and reliability checks
Drive signoff closure by identifying and resolving PV violations efficiently.
Work with physical design and layout teams to debug and fix violations.
Develop and maintain runsets, decks, and automation flows using industry-standard tools.
Analyze foundry decks and PDK updates, ensuring compliance with process requirements.
Lead tapeout readiness reviews and ensure high-quality database delivery.
Perform hierarchical verification and regression management.
Participate in improving verification methodologies, runtime, and capacity optimization.
Interface with foundry and EDA vendors to resolve tool or deck-related issues.
Mentor junior engineers and review their work as needed.
Preferred / Added Advantage Skills

Exposure to Physical Design (PD) concepts, including

Floorplanning (macro placement, block shaping, congestion awareness)
Power Delivery Network (PDN) design (power grid, IR drop considerations)

Understanding of

Placement, CTS, routing flows
PD-PV interaction and impact of layout decisions on DRC/LVS closure

Knowledge of

EM/IR, latch-up, ESD reliability checks
Multi-patterning / EUV constraints
Experience with full-chip integration and SoC-level challenges
Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
Exposure to flow automation and methodology development
Soft Skills

Strong analytical and problem-solving ability Effective communication across cross-functional teams Ownership mindset with focus on quality and timelines Ability to work independently and guide team members

More information about NXP in India...

PRINCIPAL PHYSICAL VERIFICATION ENGINEER