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Physical Verification Engineer

Mediatek • Bengaluru, Karnataka, India

onsitefull-time
Posted Oct 5, 2026Apply by Nov 4, 2026

Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implement

Full Description

Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification Coordinates with internal IP owners on IP related issues. Coordinates with Manufacturing Team on DRC related issues. Provide automation solutions to improve efficiency in tape-out flow. Report on tapeout issues. Custom Layout Requirement Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science 7+ years of physical verification or design experience Preferably well-versed in Calibre, ICV Proficient in script programming, such as, Tcl, Perl or C-shell Proficient in UNIX (Linux) platforms Track record of successful tapeout of chips Strong communication skills, problem solving and analytical skills

Physical VerificationDesign Rule Checking (DRC)Layout Versus Schematic (LVS)Antenna CheckingElectrical Rule Checking (ERC)Electrostatic Discharge (ESD) VerificationPERCCalibreICVTclPerlC ShellUNIX/LinuxTape-Out Sign-OffPlace and RouteProblem Solvingmulti-location

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