Full Description

Company Description VeriFast Technologies is a product engineering partner focused on bridging complex hardware architectures with intelligent software applications. The company delivers comprehensive “chip-to-cloud” ecosystems that optimize performance across the technology stack and support digital transformation for global enterprises. With strong capabilities in silicon engineering and turnkey ASIC solutions, VeriFast manages the full semiconductor lifecycle from RTL design and verification through to GDSII implementation and FPGA prototyping. The team has deep expertise in advanced technology nodes, including TSMC 16nm, 7nm, 5nm, and 3nm, enabling power-efficient, high-performance silicon for multicore architectures and high-speed interfaces. VeriFast also develops secure edge AI and IoT solutions and applies next-generation quality engineering practices that embed AI-driven risk assessment and predictive mitigation early in the development cycle.

Role Description This is a full-time, on-site Senior Design Verification Engineer role based in Ahmedabad, Pune. The person in this role will define and execute verification plans for complex digital designs, including testbench development, stimulus creation, and coverage analysis across multiple IP blocks and subsystems. Daily responsibilities include collaborating closely with RTL design and architecture teams to understand specifications, derive verification strategies, and perform functional and formal verification to ensure design correctness. The engineer will write and debug test cases, analyze waveforms and logs, root-cause failures, and drive issues to closure in partnership with cross-functional stakeholders. Additional tasks include contributing to verification methodology improvements, mentoring junior engineers, maintaining documentation, and supporting silicon bring-up and post-silicon validation as needed.

Qualifications Strong expertise in Functional Verification and Formal Verification, including testbench development, constrained-random testing, coverage-driven verification, and assertion-based techniques. Hands-on experience in RTL Design and Debugging, with the ability to review code, identify corner cases, analyze failures, and work with designers to resolve issues efficiently. Solid understanding of Computer Architecture, including pipelines, caches, memory hierarchies, buses, and high-speed interfaces relevant to modern SoC and ASIC designs. Proficiency with industry-standard verification tools and languages (e.g., SystemVerilog, UVM, simulators, formal verification tools, coverage and regression management tools). Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field, with several years of experience in ASIC/SoC design verification. Ability to interpret specifications, write clear documentation, and collaborate effectively with cross-functional teams in a fast-paced engineering environment. Experience with advanced technology nodes, low-power design techniques, and FPGA prototyping or emulation is a plus. Strong analytical mindset, attention to detail, and commitment to