**Role & seniority: ** Senior Digital/AMS Design Engineer (Digital RTL/Integration; ~5–8+ years)

**Stack/tools: **

HDL: SystemVerilog/Verilog (synthesis, RTL design)
Timing/implementation: STA, SDC constraints, high-speed clock domains, CDC analysis
Validation/lab automation: Python-based lab/debug tools; RTL feature exercising, CSR/Register debug
Lab debug: logic analyzers, high-speed oscilloscopes; JTAG, I2C, SPI
Other: Verilog-A modeling (preferred); Perl (preferred)
Top 3 responsibilities:
- Develop/integrate RTL for Digital-Analog Wrapper (control loops, calibration engines, high-speed data paths in 10G+ SerDes)
- Define/implement mixed-signal digital interfaces to ADCs/PLLs/driver stages; manage asynchronous domain crossings
- Own timing closure to lab validation, including silicon bring-up support and simulation-driven functional correctness
Must-have skills:
- Advanced SystemVerilog/Verilog RTL proficiency
- Strong STA/timing closure experience; working knowledge of SDC and CDC
- Python (or equivalent) for hardware control/test automation and lab debugging
- Lab debugging capability (logic analyzer/scope; JTAG/I2C/SPI)
Nice-to-haves:
- Automotive Ethernet/10GBase-T/ASA experience
- Knowledge of AFE handoff with digital logic
- DFT/BIST insertion for high-speed links
- Ability to create Verilog-A models
Location & work type:
- **Californ

Full Description

We are seeking a Senior Digital/AMS Design Engineer to drive the integration of complex digital logic into our industry-leading Automotive SerDes transceivers. In this role, you will be responsible for the RTL design of the "Digital-Analog Wrapper," ensuring seamless control and data flow between high-speed analog front-ends and the DSP/Link-layer logic. You will own the path from RTL through timing closure and support the validation of that logic in the lab.

Key Responsibilities

RTL Design & Integration: Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high-speed data paths in 10G+ transceivers.

Mixed-Signal Interface: Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing between asynchronous domains.

Timing Closure & Synthesis: Lead the digital implementation flow, working closely with the physical design team to achieve timing closure in high-speed clock domains.

Silicon Validation: (40% Lab Focus) Partner with the validation team to bring up silicon. Use Python-based tools to exercise RTL features, debug state machines, and verify registers (CSRs) in real-time hardware.

Functional Correctness: Execute block-level and chip-level simulations to ensure digital control logic correctly handles analog PVT variations and startup sequences.

Skills & Qualifications

Education: BSEE/MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration.

HDL Expertise: Advanced proficiency in SystemVerilog/Verilog for synthesis.

Timing & Implementation: Strong understanding of Static Timing Analysis (STA), clock domain crossing (CDC), and constraints (SDC).

Scripting & Automation: Deep experience with Python or Perl for hardware control, test automation, and data processing.

Lab Skills: Proficient in using logic analyzers, high-speed scopes, and JTAG/I2C/SPI protocols for on-chip debugging.

Preferred Experience

Experience with 10GBase-T, ASA, or Automotive Ethernet standards. Familiarity with the hand-off between digital logic and high-speed Analog Front Ends (AFE). Knowledge of DFT (Design for Test) and BIST (Built-In Self-Test) insertion for high-speed links. Able to create Verilog-A models

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.

Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is

$166,200 to $228,500 annually

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

Senior Digital/AMS Validation and Integration Engineer

Full Description