ASIC Design Verification Engineer, Google TPU
Google • Sunnyvale, California, United States
Salary: USD 138,000 - 197,000 / year
**Role & seniority: ** ASIC Design Verification Engineer (mid-level; ~4+ years design verification).
**Stack/tools: ** SystemVerilog/Verilog; UVM; constrained-random verification; industry-standard simulators; revision control systems; regression systems; ASIC standard interfaces.
**Top 3 responsibilities: **
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Plan verification for complex digital design blocks; work with design engineers to define key scenarios.
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Build verification environment (constrained-random with SystemVerilog/UVM) and create coverage for stimulus/corner cases.
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Debug and close coverage (identify verification holes; track progress toward tape-out).
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Must-have skills:
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4+ years in design verification.
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SystemVerilog/Verilog proficiency.
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Ability to write/close coverage and debug verification with design engineers.
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Create constrained-random verification environments using SystemVerilog/UVM.
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Nice-to-haves:
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6+ years silicon design verification experience.
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Master’s/PhD with emphasis in computer architecture.
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Experience contributing across full design + verification lifecycle.
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Knowledge of ASIC standard interfaces.
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Experience with industry simulators, revision control, and regression systems.
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Location & work type: United States; work type not specified in text.
Full Description
MINIMUM QUALIFICATIONS
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
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4 years of experience with design verification.
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Experience with SystemVerilog/Verilog.
PREFERRED QUALIFICATIONS
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Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
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6 years of experience with silicon design verification.
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Experience with industry-standard simulators, revision control systems and regression systems.
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Experience contributing across the entire design and verification life cycle.
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Knowledge of ASIC standard interfaces.
ABOUT THE JOB
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will use design and verification expertise to perform direct verification in active projects using problem-solving skills.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google
[https: //www.google.com/about/careers/applications/benefits/].
RESPONSIBILITIES
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Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
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Identify and write all types of coverage measures for stimulus and corner cases.
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Debug tests with design engineers to deliver functionally correct design blocks.
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Close coverage measures to identify verification holes and to show progress towards tape-out.
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Create a constrained-random verification environment using SystemVerilog and UVM.
