Role & seniority
- Emulation Verification Engineer (seniority not explicitly stated; requires Bachelor’s + ideally relevant industry experience)
- Member of Emulation Verification team; works on large Display and Wireless SoCs
Stack/tools
- Emulation/verification: Palladium platform (mixed-signal models), standard emulator familiarity (Palladium/Veloce/Zebu), FPGA flow (Xilinx/Altera)
- HDL & verification: SystemVerilog/Verilog, UVM, SystemVerilog assertions (SVA)
- Emulation test infrastructure: emulation regression management, triage
- Modeling/interfaces: mixed-signal model integration
- Languages/scripting: C/C++ DPI, scripting (Perl/Python/TCL)
- Power/low power: UPF (UPF-based preferable)
- UVM acceleration: preferred
Top 3 responsibilities
- Port designs onto the Palladium emulation platform for verification
- Execute and iterate against a detailed emulation test plan for large Display/Wireless SoCs
- Build/extend verification environments: create testbenches (block/system level), run regressions, and triage/debug issues
Must-have skills
- SystemVerilog/Verilog and UVM (testbench creation from scratch at block/system level)
- Regression management and triaging capability
- Strong debugging/analytical skills (implied by detailed bring-up/test execution)
Nice-to-haves
- Emulation bring-up/debug/verification experience
- Understanding RTL → emulation

Full Description

Imagine what you could do at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly. We are looking for you to join our emulation team focusing on the creation, deployment, and support of advanced emulation environments. In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines. Are you ready to help us deliver the next groundbreaking Apple products?

DESCRIPTION

As a member of the Emulation Verification team, you will play a key role in utilizing Emulation for verification of large Display and Wireless SoCs. You will also be involved in the most cutting-edge technology of bringing in mixed signal models onto the Palladium platform. The overall work will involve porting the design onto the Palladium platform, followed by executing the detailed emulation test plan.

MINIMUM QUALIFICATIONS

Bachelor degree with relevant major and, ideally, relevant industry experience Experience with SystemVerilog, Verilog or UVM Experience in creating test benches from scratch (Block and System Level) Experience in Regression Management and Triaging

PREFERRED QUALIFICATIONS

Experience with bring up, debugging and verification in Emulation Understanding of the tool flow from RTL to Emulation Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow Proven Design Verification or Silicon Validation skills Experience in writing Synthesizable SystemVerilog/Verilog code and SystemVerilog assertions Experience with SystemVerilog verification environments including C/C++ DPI, UVM Experience with any Scripting (Perl/Python/TCL) Excellent analytical and debug skills Hands on usage of Low Power methodologies (UPF based preferably) Experience in UVM Acceleration

Emulation Verification Engineer (Japan Design Center)

Full Description