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Infineon Technologies • Hanoi, Ha Noi, Vietnam
Role & seniority
DFT Design Engineer, 1–3 years of relevant experience
Location: Hanoi, Vietnam
Work type: not specified in listing
Stack/tools
RTL design and verification (logic implementation and gate-level)
Automatic Test Pattern Generation (ATPG) and scan-based test
Test coverage analysis, pattern re-simulation (gate-level)
Post-silicon analysis interface
Scripting: Python, Perl, C-shell, TCL
Collaboration with DFT methodology experts and SoC/DFT engineers
Top 3 responsibilities
Implement and verify DFT logic in RTL and gate-level
Perform ATPG for multiple fault models (Stuck-at, Transition, IDDQ, etc.) and optimize test coverage
Drive automation and process improvements; interface with test engineering and cross-functional teams; support post-silicon analysis
Must-have skills
Bachelor’s degree or higher in Electrical Engineering, Computer Science, or related field
1–3 years of DFT experience with specific flows/tools
Hands-on RTL design and verification; experience with scan implementation and ATPG
Strong understanding of IC design flow from spec to silicon debugging
Proficient in scripting (Python, Perl, C-shell, TCL)
Fluent English
Nice-to-haves
Experience with post-silicon debugging interfaces
Broader IC design knowledge and exposure to DFT methodology and SoC-level integration
Additional scripting/automation skills or domain-specific tooling
Location & work type
Hanoi, Vietnam
On-site/work type not explicitly specifi
We are looking forward to working a bright and passionate talent specialized in Design-For-Test (DFT) at Hanoi, Vietnam.
Your Role
Key responsibilities in your new role
Implementation and verification of DFT Logic in RTL and gate-level Automatic Test Pattern Generation for different fault model (StuckAt, Transition, IDDQ, etc.) Test coverage analysis and optimization Pattern re-simulation and gate level re-simulation Interface to test engineering for post silicon analysis Cooperation with design implementation, function verification team, and System-on-Chip and Design-For-Test concept engineers Automation of processes to increase efficiency Close collaboration with the DFT methodology experts and driving continuous improvement
Your Profile
Qualifications and skills to help you succeed
Bachelor's Degree or above in Electrical Engineering, Computer Science, or similar domain 1-3 years of experience in Design-For-Test (DFT) and with specific flows and tools Hands-on experience with RTL design and verification Practical experience with scan implementation and Automatic Test Pattern Generation (ATPG) Good knowledge in overview of IC design Very good understanding of the digital design flow from specification until silicon debugging Good knowledge in scripting (e.g. Python, Perl, C-shell, TCL) for automation Fluent English language skills
#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?
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