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🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
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Meta • Sunnyvale, California, United States
- Role & seniority: Hardware verification engineer (senior/lead level) focusing on SoC and core IP verification. - Stack/tools: SystemVerilog, C, C++; scripting in Python, TCL, Perl, Shell; UVM …
Salary: $136,926 - $162,580 / year
Meta • Taipei, Taiwan
- Role & seniority: Silicon Engineer (mid-level to senior) at Meta; 2+ years in silicon design/validation; capable of leading verification and pre-silicon efforts. - Stack/tools: ASICs …
Meta • Taipei, Taiwan
- Role & seniority: Senior Silicon Engineer (6+ years), working on ASICs and SoCs at Meta’s silicon teams. - Stack/tools: ASIC/SoC design and validation; EDA tools; RTL …
Meta • Sunnyvale, California, United States
- Role & seniority: ASIC verification engineer (mid-level to senior, with ~3+ years in verification) - Stack/tools: Verilog, SystemVerilog/UVM; block/IP/sub-system and SoC verification; EDA …
Salary: $186,000 - $192,170 / year
Meta • Bengaluru, Karnataka, India
- Role & seniority: Senior ASIC verification engineer (8+ years experience required; preferred 15+ years in UVM-based verification environments) - Stack/tools: SystemVerilog/UVM/OVM; C/C++; IP/sub …
Meta • Menlo Park, California, United States
- Role & seniority: Senior QA Engineer / QA Lead focusing on WhatsApp mobile app quality and QA process ownership - Stack/tools: Mobile (iOS, Android); Web technologies (HTML, CSS, REST …
Salary: $195,602 - $221,100 / year
Meta • Redmond, Washington, United States
- Role & seniority: Senior silicon engineer (6+ years) at Meta Silicon Engineering; focus on ASICs/SoCs across Infrastructure, Reality Labs, and Research. - Stack/tools: ASIC/SoC design and …
Salary: $146,000 - $209,000 / year
Meta • Bengaluru, Karnataka, India
- Role & seniority: ASIC Design Verification Engineer (Infrastructure org) for data-center ASIC/SoC projects; seniority not explicitly stated. - Stack/tools: SystemVerilog, UVM, OVM; C/C++ verification; IP …
Meta • Sunnyvale, California, United States
- Role & seniority - Product Validation Engineer (2+ years experience) at Meta - Stack/tools - System verification/validation methodologies for hardware products - Metrology, system logs, software traces, customer feedback - Internal …
Salary: $118,000 - $170,000 / year
Meta • Austin, Texas, United States
- Role & seniority: ASIC Design Verification Engineer (mid-level, 2+ years of experience in verification) - Stack/tools: SystemVerilog/UVM; C/C++; EDA tools; test bench development; scripting (Python …
Salary: $114,000 - $172,000 / year
Meta • New York, New York, United States
- Role & seniority: Engineering Manager (senior leadership), product-focused signal processing and sensor development - Stack/tools: wearables hardware; sensors (biosensors, ECG/PPG, capacitive sensing, EMG); ML/AI; signal …
Salary: $184,000 - $257,000 / year
Meta • Austin, Texas, United States
- Role & seniority: Senior ASIC Engineer (Infra). Part of Infrastructure Silicon Enablement; focus on pre/post-silicon validation for data center applications. - Stack/tools: - Languages: Python, C/C …
Salary: $178,000 - $250,000 / year
Meta • Redmond, Washington, United States
- Role & seniority: Verification Engineer (mid-level), 2+ years experience - Stack/tools: SystemVerilog/UVM, C/C++, block/IP/SoC verification; EDA tools; scripting (Python, TCL, Perl, Shell); version …
Salary: $114,000 - $172,000 / year
Meta • Sunnyvale, California, United States
- Role & seniority: Product Validation Engineer; mid-level (2+ years in validation/engineering), with potential for higher levels with 4+ years. - Stack/tools: hardware/software/content integrated validation …
Salary: $118,000 - $170,000 / year
Meta • Bengaluru, Karnataka, India
- Role & seniority: Senior/Lead ASIC Design Verification Engineer (12+ years; advanced/lead level; potential for broader leadership) - Stack/tools: - HDL/verification: Verilog, SystemVerilog, UVM (OVM), C/C …
Meta • Austin, Texas, United States
- Role & seniority: Senior/Staff ASIC Formal Verification Engineer (Infrastructure group) - Stack/tools: Formal verification for IP/SoC; SystemVerilog, SVA; Datapath, sequential equivalence, Xprop, Clock Gating; EDA tools …
Salary: $178,000 - $250,000 / year
Meta • Redmond, Washington, United States
- Role & seniority: Senior/experienced verification engineer (6+ years in DV) - Stack/tools: SystemVerilog/UVM-based verification; IP/sub-system/SoC verification; C/C++; EDA tools; scripting in …
Salary: $146,000 - $209,000 / year
Meta • Austin, Texas, United States
- Role & seniority: ASIC Design Verification Engineer, senior-level (8+ years) in Meta’s Infrastructure organization. - Stack/tools: SystemVerilog/UVM/OVM; C/C++; SV Assertions; Formal; Emulation; EDA …
Salary: $178,000 - $250,000 / year
Meta • Bengaluru, Karnataka, India
- Role & seniority: ASIC Engineer, Infra Silicon Enablement; mid-to-senior level (6+ years in ASIC/Pre-Post Silicon validation) - Stack/tools: Python, C/C++ (and data structures …
Meta • Bengaluru, Karnataka, India
- Role & seniority: Application-Specific Integrated Circuit (ASIC) Design Verification Engineer; mid-to-senior level (5+ years; preference for 8+ years in some qualifications) - Stack/tools: SystemVerilog, UVM …
