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Retym • Austin, Texas, United States
Role & seniority: Verification Team-Leader with 10+ years in digital design verification; 3+ years managing/leading verification teams.
Stack/tools: SystemVerilog, UVM; verification environments; VLSI verification flows; interfaces with algorithmic models and software; (eRM/OVM as referenced methods).
Lead, mentor, and manage the verification team to meet milestones and deliverables; plan and allocate resources.
Define and execute verification strategies/plans for complex digital blocks and systems; drive functional and coverage-based verification across cycles.
Oversee development of robust, reusable verification environments; review/approve plans, testbenches, and coverage; report progress and risks to management.
10+ years in digital design verification; 3+ years in a leadership/line-management role.
Proven track record completing two or more full block/system verification cycles.
Deep knowledge of VLSI verification flows and methodologies; expertise in SystemVerilog/UVM (and/or eRM/OVM); experience across block, cluster, and full-chip verification; strong debugging and leadership/communication abilities.
Experience with high-speed protocols (Ethernet, PCIe, SerDes); scripting for automation (Python, Perl).
Familiarity with formal verification, system-level verification, post-silicon validation; project planning tools/methodologies.
Location & work type: Location not specif
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects.
Requirements Key Responsibilities Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables. Define and execute verification strategies and plans for complex digital blocks and systems. Oversee the development of robust and reusable verification environments using SystemVerilog and UVM. Review and approve verification plans, testbenches, and coverage metrics. Drive functional and coverage-based verification across multiple block/system verification cycles. Collaborate with design engineers to debug and resolve functionality issues. Ensure effective resource allocation and project planning to achieve optimal results. Foster a culture of technical excellence, continuous learning, and innovation within the team. Report verification progress, issues, and risks to senior management and other stakeholders. Required Qualifications 10+ years of experience in digital design verification—a must. 3+ years of experience managing or leading verification teams. Proven track record of completing two or more full block/system verification cycles. In-depth knowledge of VLSI verification flows, concepts, methodologies and interfaces with algorithmic models and SW. Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM). Experience in block, cluster and full chip verification levels. Strong problem-solving skills and the ability to debug complex functionality issues. Excellent leadership, communication, and organizational skills to manage and inspire a team.
Preferred Qualifications Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes. Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes. Familiarity with formal verification techniques and tools. Background in system-level verification or post-silicon validation. Experience with project planning tools and methodologies for effective team management.