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European Tech Recruit • Athens, Attica, Greece
Role & seniority: Team Lead Verification Engineer (senior level), on-site in Athens
Stack/tools: Digital verification (UVM), Cadence Xcelium, vManager/eManager, SystemVerilog, verification methodologies (functional, ABV, formal, regression), FPGA-based verification; strong digital design background (mixed-signal/analog software)
Lead and manage a hands-on verification team; coordinate tasks, mentor, and drive professional development
Own verification quality, schedules, and deliverables; ensure goals for cost, timeline, functionality, and performance are met
Define and execute verification strategies (plans, testbench architecture, component development) and collaborate with design and verification result reviews
10+ years in digital verification with 10+ years of hands-on UVM expertise; ability to build UVM environments from specification to final verification report
Strong knowledge of verification methodologies and platforms; proficiency with Cadence Xcelium, vManager/eManager, SystemVerilog
Solid digital design background; experience across mixed-signal, software, digital radio, or analog-related projects
Excellent communication, leadership, and stakeholder-influencing skills; fluent English
Wireless connectivity experience
Scripting: TCL, Make, Perl
Greek language proficiency
Location & work type: On-site opportunity in Athens; full rights to work must be in place
A leading semiconductor company based in Athens are seeking to bolster their team with an experienced team lead verification engineer
Please note this is an on-site opportunity based in Athens. Full rights to work must already be in place before applying.
Lead and manage a hands-on verification team, including task coordination, performance management, mentoring, and professional development Own verification quality, schedules, and deliverables, ensuring project goals for cost, timeline, functionality, and performance are met Define and execute verification strategies, including verification plans, testbench architecture, component development, and proof of design correctness against specifications Drive continuous improvements in verification efficiency, reusability, and design-for-verification practices, including make-or-buy decisions for verification solutions Collaborate closely with design teams through specification reviews, design reviews, and verification result reviews to improve overall product quality
10+ years of experience in digital verification, including 10+ years of hands-on UVM expertise and the ability to build UVM environments from specification to final verification report Strong knowledge of verification methodologies and platforms (functional verification, ABV, formal verification, regression frameworks, FPGA-based verification), using tools such as Cadence Xcelium, vManager/eManager, and SystemVerilog Solid intermediate-to-advanced digital design background, with experience across mixed-signal, software, digital radio, or analog-related projects Excellent communication, leadership, and interpersonal skills, with the ability to influence peers and stakeholders through technical expertise Fluency in English (written and spoken); additional skills such as wireless connectivity experience, scripting (TCL/Make/Perl), or Greek language proficiency are advantageous
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.
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