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Infineon Technologies • Bengaluru, Karnataka, India
Role & seniority: Verification Engineer (senior level)
Stack/tools: Universal Verification Methodology (UVM); SystemVerilog; Constrained Random testing; UPF for low-power verification; VHDL; Cadence verification software; microcontroller-based ICs; firmware/RTL knowledge
Design and develop the IC verification environment using UVM; drive verification methodology and plan, in collaboration with other disciplines
Implement test scenarios (SystemVerilog) and verify functionality with constrained random approaches; identify sub-modules suitable for formal verification and apply it
Advise/support business units, disseminate know-how, and optimize verification methodology/coverage integrated into the design system; verify low-power aspects with UPF
Degree in Electrical Engineering, Computer Science, or related field
5+ years in Metric Driven Verification (digital & mixed-signal) and Formal Verification
Experience with microcontroller-based ICs; firmware/RTL (VHDL)
Strong UVM and UPF expertise; ability to create and disseminate verification methods
Cadence verification software experience preferred
Some technical leadership and project management experience
Experience with security and safety requirements
Deeper Cadence toolchain familiarity beyond basic use
Location: not specified
Work type: not specified
Job Description
Be in continuous and intensive contact with our development sites worldwide; Advise and support the experts from our business units in verification projects; Drive the internal exchange of know-how and experience at Infineon; Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineon's design system and supporting their implementation in the development of new products; Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan; Design and develop the verification environment for ICs using the"Universal Verification Methodology" (UVM); Independently identify sub-modules that are particularly suitable for formal Verification and apply this methodology; Implement test scenarios using SystemVerilog and verify functionality using a Constrained Random Approach; Use the Unified Power Format (UPF) to verify the low-power aspects of our designs;
Your Profile
#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?
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