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Infineon Technologies • Bengaluru, Karnataka, India
Role & seniority: Senior/Lead verification engineer with at least 5 years’ experience; some initial technical leadership and project management exposure
Stack/tools: Universal Verification Methodology (UVM); SystemVerilog; UPF (low-power verification); formal verification; constrained random testing; VHDL; Cadence verification software (a plus)
Design and development of the IC verification environment and methodology (UVM) and integrate results into Infineon’s design system
Implement test scenarios in SystemVerilog (constrained random) and apply formal verification to sub-modules; verify functionality
Verify low-power aspects using UPF; collaborate with other disciplines to define verification plans and optimize verification coverage
Degree in Electrical Engineering, Computer Science, or related field
5+ years in metric-driven verification (digital & mixed-signal) and formal verification
Strong UVM and UPF expertise; experience with firmware/RTL design (VHDL)
Experience with microcontroller-based ICs; understanding of security/safety requirements
Ability to create and disseminate verification methods; some technical leadership/project management experience
Cadence verification software experience
Deeper firmware and RTL (VHDL) proficiency; hands-on leadership in projects
Location & work type: Location not specified; work type not stated in the description
Job Description
Be in continuous and intensive contact with our development sites worldwide; Advise and support the experts from our business units in verification projects; Drive the internal exchange of know-how and experience at Infineon; Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineon's design system and supporting their implementation in the development of new products; Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan; Design and develop the verification environment for ICs using the"Universal Verification Methodology" (UVM); Independently identify sub-modules that are particularly suitable for formal Verification and apply this methodology; Implement test scenarios using SystemVerilog and verify functionality using a Constrained Random Approach; Use the Unified Power Format (UPF) to verify the low-power aspects of our designs;
Your Profile
#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?
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