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Infineon Technologies • Bengaluru, Karnataka, India
Role & seniority: Senior Verification Engineer (5+ years in Metric-Driven Verification and Formal Verification)
Verification: UVM, SystemVerilog, Constrained Random, UPF
Design: RTL/VHDL
Tools: Cadence verification software (plus general Cadence ecosystem)
Domains: microcontroller-based ICs, security and safety requirements
Design and develop the verification environment for ICs using UVM
Define verification methodology and verification plan; optimize coverage and integrate results into Infineon’s design system
Identify sub-modules suitable for formal verification; implement formal verification and develop test scenarios; verify low-power aspects with UPF
Degree in Electrical Engineering, Computer Science, or related field
5+ years in metric-driven verification (digital & mixed-signal) and formal verification
Experience with microcontroller-based ICs; knowledge of security and safety requirements
Expertise in UVM and UPF; firmware and RTL design (VHDL)
Cadence verification software experience; some technical leadership or project management exposure
Additional leadership or project management experience
Deeper experience with security/safety-critical verification
Strong cross-disciplinary collaboration (e.g., with Application Engineering)
Location & work type: Location and work type not specified in the description.
Job Description
Be in continuous and intensive contact with our development sites worldwide; Advise and support the experts from our business units in verification projects; Drive the internal exchange of know-how and experience at Infineon; Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineon's design system and supporting their implementation in the development of new products; Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan; Design and develop the verification environment for ICs using the"Universal Verification Methodology" (UVM); Independently identify sub-modules that are particularly suitable for formal Verification and apply this methodology; Implement test scenarios using SystemVerilog and verify functionality using a Constrained Random Approach; Use the Unified Power Format (UPF) to verify the low-power aspects of our designs;
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As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
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