Role & seniority: Senior Design Verification Engineer (R&D/Verification focus)

Stack/tools: RTL verification (SystemVerilog, Specman/E), UVM; CPU/SOC/SoC IP verification; constrained-random test environments; scripting (Python, Perl, Shell) a plus

Top 3 responsibilities

Plan and execute verification of digital design blocks, defining key verification scenarios
Develop/refine random verification environments (SystemVerilog/UVM or Specman) and implement coverage measures
Drive coverage analysis, debug tests with design engineers, and push verification towards tape-out

Must-have skills

8+ years of RTL verification experience with SystemVerilog or Specman/E for FPGAs/ASICs
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, memory subsystems)
Experience creating/using verification components and environments in standard methodologies
Bachelor’s degree in Electrical Engineering or equivalent practical experience

Nice-to-haves

Master’s degree (Electrical Engineering or Computer Science)
Experience with UVM; proficiency in SystemVerilog; scripting languages (Python, Perl, Shell, Bash)
Location & work type: Location not specified; full-time role

Full Description

MINIMUM QUALIFICATIONS

Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or Application-specific integrated circuit (ASICs).
Experience with Central Processing Unit (CPU ) implementation, assembly language, or compute System on a Chip (SOC).
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience creating and using verification components and environments in standard verification methodology.

PREFERRED QUALIFICATIONS

Master’s degree in Electrical Engineering or Computer Science.
Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).

ABOUT THE JOB

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Senior Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-random test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through corner-case testing.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

RESPONSIBILITIES

Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.

Senior Design Verification Engineer, Networking, Google Cloud