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Google • Bengaluru, Karnataka, India
Role & seniority: Verification Engineer, senior level (8+ years in RTL verification)
Stack/tools: SystemVerilog or Specman/E; FPGA/ASIC verification; standard simulators; revision control; regression systems; UVM; constrained-random verification
Plan the verification of digital design blocks and identify important verification scenarios
Create and manage constrained-random verification environments (SystemVerilog/UVM) and coverage measures
Debug tests with design engineers to ensure functional correctness and progress toward tape-out; measure coverage to close verification holes
Bachelor’s degree in Electrical Engineering or equivalent practical experience
~8 years of RTL verification experience (SystemVerilog or Specman/E) for FPGAs/ASICs
Verification and debugging of IP/subsystems/SoCs in Networking (e.g., packet processing, bandwidth management, congestion control)
Experience verifying digital systems with standard IP components/interconnects
Master’s degree
Experience with industry-standard simulators, version control, and regression systems
AI/ML accelerators or vector processing unit experience
Experience across full verification lifecycle; strong problem-solving and communication skills
Location & work type: not specified in provided text (location and work-type details unavailable)
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Measure to identify verification holes and to show progress towards tape-out.
Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).