🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Infineon Technologies • Bengaluru, Karnataka, India
Role & seniority
Analog IP modelling lead/co-lead role; senior engineer with mentoring responsibilities
BS/MS in Electrical Engineering; experience: Bachelor 6–11 yrs or Master 4–10 yrs
Stack/tools
Verilog, SystemVerilog (incl. UVM)
Mixed-signal DV verification
Dotlib generation; AMS/Digital Block Modelling RNM
MSV simulation flow (nice-to-have)
Automation and formal verification methodologies (nice-to-have)
Top 3 responsibilities
Plan and lead modelling of analog/hard IP using Verilog/SystemVerilog
Contribute to pre-silicon validation and modelling support development
Mentor junior engineers and collaborate with global team members
Must-have skills
Deep experience in Verilog/SystemVerilog and UVM
Modelling technique for Analog Blocks; exposure to digital verifications
Ability to work with geographically distributed teams
Experience with dotlib generation; AMS/Digital Block Modelling RNM
Nice-to-haves
Exposure to MSV simulation flow
Basic understanding of analog circuits
Experience with automation and formal verification methodologies
Location & work type
Location: not specified
Work type: not specified
Contact: Jyoti.Vimal@infineon.com
Candidate will work as part of modelling the analog IP by means of Verilog/ system Verilog and able to support DV verification for mixed signal IP.
Your Role
Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.
Good understanding of modelling technique for Analog Blocks using Verilog and System Verilog. Good exposure on digital verifications, Ability to interact and work with team member in multiple geography. Good exposure to dotlib generation.
Exposure to the MSV simulation flow. Basic understanding of analog circuits.
Your Profile
BS/MS in Electrical Engineering Bachelor's - 6 to 11 years’ experience, Master’s - 4 to 10 years’ experience. Very good knowledge of Verilog/System Verilog and UVM. Should be a good mentor and guide for junior engineers in the team. Candidate should have worked on AMS/Digital Block Modelling based RNM modelling. Exposure to deployment of automation and formal verification methodologies is a plus.
#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in?
We are on a journey to create the best Infineon for everyone.
This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.
Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.
Click here for more information about Diversity & Inclusion at Infineon. Show more Show less