Role & seniority: Senior/lead engineer focused on analog IP modelling; 6–11 yrs (Bachelor) or 4–10 yrs (Master); capable of mentoring junior engineers.

Stack/tools: Verilog and SystemVerilog (including UVM); mixed-signal DV verification; dotlib generation; MSV simulation flow (nice-to-have); AMS/Digital Block Modelling RNM modelling; exposure to automation and formal verification methodologies (nice-to-have).

Top 3 responsibilities

Lead/involve in planning the modelling of analog/hard IP using Verilog/SystemVerilog.
Develop modelling support for pre-silicon validation.
Contribute to DV verification for mixed-signal IP and collaborate with global team.

Must-have skills

Strong modelling techniques for Analog Blocks in Verilog/SystemVerilog.
Very good Verilog/SystemVerilog and UVM knowledge.
Digital verification exposure; ability to work with cross-geo teams.
Exposure to dotlib generation; basic understanding of analog circuits.
Experience in AMS/Digital Block Modelling RNM modelling.
Ability to mentor junior engineers.

Nice-to-haves

MSV simulation flow exposure.
Automation and formal verification methodologies experience.

Location & work type: Location not specified; work type not specified.

Full Description

Candidate will work as part of modelling the analog IP by means of Verilog/ system Verilog and able to support DV verification for mixed signal IP.

Your Role

Key responsibilities in your new role

Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.

MUST have

Good understanding of modelling technique for Analog Blocks using Verilog and System Verilog.
Good exposure on digital verifications,
Ability to interact and work with team member in multiple geography.
Good exposure to dotlib generation.

Added advantage

Exposure to the MSV simulation flow.
Basic understanding of analog circuits.

Your Profile

Qualifications and skills to help you succeed

BS/MS in Electrical Engineering
Bachelor's - 6 to 11 years’ experience, Master’s - 4 to 10 years’ experience.
Very good knowledge of Verilog/System Verilog and UVM.
Should be a good mentor and guide for junior engineers in the team.
Candidate should have worked on AMS/Digital Block Modelling based RNM modelling.
Exposure to deployment of automation and formal verification methodologies is a plus.

Contact

Jyoti.Vimal@infineon.com

#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Senior Analog Verification/Modelling Engineer