IP Release & Verification Engineer
AMD • Iași, Romania
Role & seniority: IP Release & Verification Engineer (mid-level) focused on Infinity (Data) Fabric IP integration.
Stack/tools: Computer architecture/digital design, verification (UVM), RTL/firmware collaboration; simulation and debug tools (VCS, Verdi, ModelSim as applicable); programming/scripting (C++, SystemVerilog, Python, Perl, Shell/Ruby); Unix/Linux; documentation tooling.
Top 3 responsibilities
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Collaborate with architects, IP designers, verification, physical design and PM to ensure smooth feature integration and timely IP releases.
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Build test plans and implement directed and random verification tests; deliver milestone drops that are complete and well-documented.
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Provide first-level integration issue triage, debugging, root-cause analysis, and maintain/update IP documentation and release notes.
Must-have skills
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Strong understanding of computer architecture, interconnects, and cache coherency.
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Experience in digital design/verification (UVM) and analysis of simulation results; familiarity with VCS/Verdi.
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Proficiency in C++ and SystemVerilog; scripting (Python, Perl); Unix/Linux environment; good written and spoken English.
Nice-to-haves
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Direct experience with Verilog simulators (ModelSim, VCS) and automation tooling; familiarity with formal verification concepts.
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Location & work type: Iasi, Hybrid work model.
Full Description
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE We are looking for an adaptive, self-motivated IP Release & Verification Engineer to join our growing team. As a key contributor in Infinity (Data) Fabric IP, you will be the critical link between the core IP development team and the various System-on-Chip (SoC) product integration teams. You will assist in preparing IP releases, validating deliverables and ensure that the IP milestone drops are high-quality, fully documented, and meet critical SoC project schedule. You will also be providing first-level support for integration issues, debug and analysis for failures. THE PERSON You are a detail-oriented engineer with a passion for modern, complex processor architecture, digital design, and/or verification in general. You have strong analytical and problem-solving skills and comfortable using industry-standard tools to ensure smooth IP integration. You are a team player who has excellent communication skills and enjoys collaborating with other engineers from different sites/time zones in a fast-paced environment. KEY RESPONSIBILITIES Collaborate with architects, IP designers, verification, physical design, and program management teams to understand new features, ensure smooth integration and timely deliver Build test plan documentation, accounting for interactions with other hardware/software features/components Write and implement both directed and random verification tests
IP Release support: milestone drop delivery to SoC team. Ensure deliverables are complete, accurate, and meet project timelines
Integration issue triage: provide first level of support for integration-related issues, helping to identify whether problems originate from IP, flow, or environment
Debug & Analysis: Use simulation and debug tools (e.g., VCS, Verdi) to analyze failures and support root cause identification Work with RTL and firmware engineers to resolve design defects Maintain and update IP documentation, including release details, integration guidelines, feature lists and known issues Ensure changelist integration Support automation efforts using scripting languages (Python, Perl) to improve release and validation flows. PREFERED SKILLS AND EXPERIENCE Good understanding of computer architecture, interconnects and cache coherency Knowledge/experience on digital design and verification processes, methodologies like UVM Ability to analyze simulation results and assist in resolving technical issues. Familiarity with simulation tools (e.g., VCS), emulation, and debug tools. Object Orientated Programming knowledge (we use C++ and System Verilog) Scripting skills (Perl, Shell, Ruby, Python) Experience working in a Unix/Linux environment Advanced verbal and written English NICE TO HAVE Direct experience with Verilog simulators (ModelSim, VCS, Eda Playground, etc.) Exposure to scripting and automation tools to streamline and enhance modeling workflows Familiarity with formal verification concepts and tools is a plus PERSONAL COMPETENCIES Analytical thinking & goal-oriented, eager to learn Self-driven, but capable of working within a team Strong desire for personal achievement Excellent communication and teamwork skills, with the ability to work with cross-functional teams in a global environment ACADEMIC CREDENCIALS Bachelor’s or master’s degree in computer engineering/computer science/electrical engineering LOCATION Iasi (Hybrid) #LI-NG2 #LI-HYBRID
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.