🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Apple • San Diego, California, United States
Role & seniority: Analog Layout Automation Engineer, mid-level (BS + ~3+ years experience)
Stack/tools: Analog/mixed-signal layout in deep-submicron CMOS/FinFET; AI/ML-enabled CAD workflows; Cadence Virtuoso (XL, EAD, APR, Constraint Manager), Cadence Innovus; PCell creation; scripting in SKILL, Perl, TCL, Shell, Python; PyTorch; LVS/DRC/ERC verification; layout automation and data analysis
Translate design concepts into silicon through analog/mixed-signal layout and verification (LVS/DRC/ERC)
Review floor plans, analyze circuits, run verification suites, and resolve layout issues
Drive automation: develop scripts, optimize workflows, and apply AI/ML for layout quality, verification acceleration, and data-driven insights
BS degree with ~3+ years relevant industry experience
Experience designing analog/mixed-signal layouts in deep-submicron CMOS/FinFET
Programming/scripting proficiency (SKILL, Perl, TCL, Shell, Python) for automation and data analysis
Strong knowledge of NC/DFM, device matching, noise, power, IR drop, RC delay, electromigration
Proficiency with Cadence Virtuoso and Cadence Innovus; PCell creation; floor planning; LVS/DRC/ERC interpretation
Ability to work across cross-functional teams and communicate effectively
Experience with AI/ML for layout optimization; CNNs; supervised/self-supervised learning; PyTorch
Advanced image processing concepts, spatial
Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency.
DESCRIPTION
As an Analog Layout Automation Engineer, you’ll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You’ll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights.
MINIMUM QUALIFICATIONS
BS and a minimum of 3 years relevant industry experience.
PREFERRED QUALIFICATIONS
Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks using scripting and CAD tools. Proven record in implementing high-quality analog layouts with tight device matching, low noise, and low power consumption. Familiarity with failure-prone circuit/layout structures, analog and DFM best practices, and the ability to diagnose and resolve layout-related issues. Strong proficiency in custom and standard-cell floor planning, hierarchical layout assembly, and physical integration. Understanding of image processing fundamentals, spatial representations, multi-channel image handling, segmentation, and object detection concepts. Technical understanding of IR drop, RC delay, electromigration, self-heating, coupling capacitance, and related reliability concerns. High proficiency in interpreting physical verification reports, including DRC, ERC, and LVS. Experience using advanced Cadence Virtuoso features (XL, EAD, APR, Constraint Manager), and familiarity with Cadence Innovus. Experience with CAD automation workflows and PCell creation. Excellent communication skills and the ability to work effectively with cross-functional teams.