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Neuralink • Fremont, California, United States
Salary: $125,000 - $233,000 / year
Role & seniority: Senior/Staff analog & mixed-signal IC design engineer (5+ years post-BS); BS required; MS/PhD preferred.
Stack/tools: Analog CMOS design (delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, audio CODECs, high-speed PHY/SERDES); transistor-level design and verification; layout coordination; Verilog-AMS, SystemVerilog; scripting/automation; FinFET technologies; lab testing for high-precision ICs; design-for-high-volume production.
Design analog/mixed-signal circuits and subsystems from circuit-level to layout to meet noise, mismatch, distortion, power, and cost requirements.
Oversee block-level layout with layout teams; plan and execute analog verification (power, performance, linearity, yield) with complex simulations.
Mentor/test junior engineers; run tests, identify issues, and coordinate with internal/external users and vendors to align implementations.
BS in electrical engineering or related field with 5+ years in analog/mixed-signal CMOS design and silicon validation.
Experience with relevant IP blocks (ADC/DAC, VCO/PLL, SERDES, etc.); strong verification and simulation capability.
Ability to plan verification, perform complex analyses, and collaborate across design and layout.
MS/PhD; experience in high-volume production; lab testing of high-precision analog/mixed-signal ICs; Verilog-AMS/SystemVerilog modeling; advanced CMOS FinFET design and layout.
Scripting/a