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Etched • San Jose, California, United States
Salary: $200,000 - $300,000 / year
Role & seniority: Head of Design Verification – Interface IP; senior technical lead with hands-on ownership of DV strategy, execution, and tape-out sign-off for key Interface IP subsystems.
Stack/tools: SystemVerilog, UVM; verification environments for CPU subsystems, high-speed interfaces (PCIe, Ethernet, AXI/AMBA); emulation and formal verification exposure; vendor IP integration and configuration reviews; pre-silicon validation.
Own end-to-end DV strategy and sign-off for Interface IP across Etched SoCs; technical authority on correctness, protocol compliance, performance, and robustness.
Lead DV for CPU subsystems (boot, interrupts, coherency, system control) and high-speed interfaces (throughput/latency verification); architect/evolve verification environments.
Drive vendor IP integration, gap closure, and emulation planning; hire/mentor a small Interface IP DV team; collaborate with architecture, RTL, SoC DV, and software teams; tape-out sign-off.
10+ years design verification with ownership of complex IP or SoC subsystems.
Deep hands-on SystemVerilog and UVM expertise.
Strong understanding of SoC mCPU design and high-speed interfaces (PCIe, Ethernet, AXI/AMBA).
Tape-out experience with final DV sign-off responsibility; systems-level DV mindset.
Comfortable in a fast-moving startup environment.
About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Job Summary We are hiring a Head of Design Verification – Interface IP to own and scale verification for all major interface IP subsystems across Etched silicon. This is a hands-on technical leadership role: you will manage a small team while personally owning DV strategy, execution, and tape-out sign-off for critical subsystems including CPU subsystems, HBM memory controllers, PCIe, Ethernet, and system peripherals. You will lead Interface IP DV from architecture definition through tape-out, working closely with RTL designers, IP vendors, SoC and performance DV, software, and architecture teams. You will set standards, define best practices, and ensure verification quality scales with increasingly ambitious chips. Key responsibilities
Own end-to-end DV strategy and sign-off for Interface IP across Etched SoCs
Act as the technical authority on correctness, protocol compliance, performance, and robustness
Lead DV for CPU subsystems (boot, interrupts, coherency, system control)
Lead DV for high-speed interfaces, including throughput and latency verification
Architect and evolve SystemVerilog/UVM verification environments
Drive vendor IP integration, configuration reviews, and verification gap closure
Partner closely with architecture, RTL, SoC DV, and software teams
Hire, mentor, and lead a small, high-impact Interface IP DV team
Advise the strategy and execution of emulation testing for pre-silicon validation
You may be a good fit if you have
10+ years of design verification experience with ownership of complex IP or SoC subsystems
Deep hands-on expertise in SystemVerilog and UVM
Strong understanding of SoC mCPU design and high-speed interfaces (PCIe, Ethernet, AXI/AMBA)
Tape-out experience with final DV sign-off responsibility
Systems-level DV mindset
Comfortable being hands-on in a fast-moving startup environment
Strong candidates may also have experience with
Experience leading DV teams at Apple, NVIDIA, Broadcom, AMD, or similar
Vendor IP evaluation and integration experience
Exposure to formal verification, emulation, or silicon bring-up
Power-aware or low-power interface verification
Benefits
Full medical, dental, and vision packages, with generous premium coverage
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to San Jose (Santana Row)
Compensation
$200,000 - $300,000
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.