Role & seniority: Design Verification Lead (DV Lead) in Qualcomm Israel; hands-on technical leadership of a small DV team.

Stack/tools: UVM-based constrained‑random verification; SystemVerilog; testbench architecture (agents, sequences, scoreboards, coverage); Python/Perl/Tcl/shell; UNIX/Linux.

Top 3 responsibilities

Define verification strategy, test plan, and coverage goals for complex peripheral IP/subsystems.
Architect, develop, and maintain UVM verification environments; drive debug across RTL, testbench, and system level.
Lead day‑to‑day DV activities (planning, code/testplan reviews, mentoring) and drive quality metrics toward tape‑out; contribute to methodology improvements.

Must-have skills

BSc/MSc in Electrical/Computer Engineering or related field; 7+ years hands‑on verification with UVM/SystemVerilog.
Strong digital design/SoC/IP architecture knowledge.
Proven technical leadership and ability to lead/mentor a small DV team.
Proficiency in UVM testbench architecture, constrained‑random, coverage‑driven verification, and debugging large regressions.
Scripting in Python/Perl/Tcl/Shell; UNIX/Linux environment.

Nice-to-haves

Experience with high‑speed peripherals (USB, PCIe, Display, SerDes, or similar I/O IP).
Knowledge of low‑power, reset, and clock‑domain interactions at IP/SoC level.
Experience with regression management, metrics, sign‑off criteria; cross-site collaboration.
Location & work type: Haifa, Isr

Full Description

Company

Qualcomm Israel Ltd.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm’s Peripheral IP organization is looking for a hands‑on Design Verification Lead to drive verification of next‑generation wired/wireless peripheral subsystems that power Snapdragon platforms.
As a DV Lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute UVM‑based verification strategy, and lead a small team of talented engineers to first‑time‑right silicon.
This is a 5 days on site position in Haifa
What you’ll do
Define verification strategy, test plan, and coverage goals for complex peripheral IP and subsystem blocks
Architect, develop, and maintain UVM‑based constrained‑random verification environments

Lead day‑to‑day activities of a small DV team: task planning, code and testplan reviews, mentoring, and technical guidance Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams Analyze and close functional and code coverage, drive quality metrics to tape‑out criteria Contribute to methodology and flow improvements across the Peripheral DV team Minimum qualifications BSc/MSc in Electrical/Computer Engineering or related field At least 7 years of hands‑on verification experience using UVM and SystemVerilog Strong background in digital design and SoC/IP architecture

Proven technical leadership

Prior experience leading or mentoring engineers or
Demonstrated ability and motivation to lead a small DV team (e.g., ownership of major IP, driving cross‑functional efforts)

High technical proficiency in

UVM testbench architecture (agents, sequences, scoreboards, coverage)
Constrained‑random, coverage‑driven verification
Debugging complex failures in large‑scale regressions
Scripting (Python/Perl/Tcl/shell) in a UNIX/Linux environment
Preferred qualifications
Experience with high‑speed peripherals (e.g., USB, PCIe, Display, SerDes, or similar I/O IP)
Knowledge of low‑power, reset, and clock‑domain interactions at IP/SoC level
Familiarity with regression management, metrics, and sign‑off criteria
Experience working with global, cross‑site teams
What we offer
Opportunity to own verification of cutting‑edge peripheral IP used in high‑volume products
A strong technical environment with the ability to lead, influence, and mentor

Design Verification Lead – Peripheral IP Group (UVM) - Haifa, Israel