Role & seniority: Senior Design Verification Engineer (full-time) in Qualcomm Israel, on-site in Haifa.

Stack/tools: SystemVerilog, UVM; constrained-random testing; coverage-driven verification; testbench architectures (agents/sequences/scoreboards); debugging across large regression environments; scripting in Python/Perl/Tcl/shell; Linux/UNIX.

Top 3 responsibilities

Verify IP and subsystem peripherals integrated into complex SoCs; own end-to-end verification (testplan, execution, coverage closure).
Develop/maintain UVM verification environments with constrained-random testing, assertions, and coverage models.
Collaborate with design, architecture, software, and validation teams; serve as DV methodology technical focal point (debug and quality).

Must-have skills

BSc/MSc in Electrical or Computer Engineering (or related).
5+ years of hands-on design verification using SystemVerilog and UVM.
Strong digital design fundamentals; SoC/IP‑level architectures understanding.
UVM testbench architecture, constrained-random and coverage-driven verification.
Debugging in large regression environments; scripting in Python/Perl/Tcl/shell; Linux/UNIX.

Nice-to-haves

Potential for technical or team leadership growth.
Experience with high-speed peripheral IPs (USB, PCIe, Display, SerDes) or similar I/O subsystems.
Knowledge of low-power design, reset sequencing, clock-domain interactions at IP/SoC level.
Regression management, verific

Full Description

Company

Qualcomm Israel Ltd.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm’s Peripheral IP organization is looking for a Senior Design Verification Engineer to develop the next generation of wired and wireless peripheral subsystems that power Snapdragon® platforms.
This is a full‑time, 5 days on site position in Haifa.
What You’ll Do
Verify IP and subsystem level peripherals integrated into complex SoCs
Own end‑to‑end verification, including testbench architecture, test planning, execution, and coverage closure
Develop and maintain UVM/SystemVerilog verification environments using constrained‑random testing, assertions, and coverage‑driven methodologies
Collaborate closely with design, architecture, software, and validation teams across multiple sites
Act as a technical focal point for DV methodology, debug, and verification quality
Minimum Qualifications
BSc or MSc in Electrical Engineering, Computer Engineering, or a related field
5+ years of hands‑on design verification experience using SystemVerilog and UVM
Strong understanding of digital design fundamentals and SoC / IP‑level architectures

Proven technical proficiency in

UVM testbench architecture (agents, sequences, scoreboards, coverage models)
Constrained‑random and coverage‑driven verification
Debugging complex issues in large‑scale regression environments
Scripting and automation using Python, Perl, Tcl, or shell in a Linux/UNIX environment
Preferred Qualifications
Motivation and potential to grow into a technical or team‑lead role over time
Experience with high‑speed peripheral IPs such as USB, PCIe, Display, SerDes, or similar I/O subsystems
Knowledge of low‑power design, reset sequencing, and clock‑domain interactions at the IP or SoC level
Familiarity with regression management, verification metrics, and sign‑off criteria
Experience working effectively with global, cross‑site teams
What We Offer
Opportunity to verify cutting‑edge peripheral IP used in high‑volume, industry‑leading products
A strong technical environment with opportunities to lead, influence, and mentor
Close collaboration with world‑class design, architecture, CAD, and validation teams
A clear growth path toward senior technical leadership or people management within Qualcomm

Senior Design Verification Engineer - Haifa, Israel