🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Meta • Bengaluru, Karnataka, India
Role & seniority: Application-Specific Integrated Circuit (ASIC) Design Verification Engineer; mid-to-senior level (5+ years; preference for 8+ years in some qualifications)
Stack/tools: SystemVerilog, UVM (and OVM), C/C++, IP/SoC verification; Formal, Emulation; EDA tools; scripting (Python, TCL, Perl, Shell); revision control (Git, Mercurial, SVN); experience with high-speed interfaces (AMBA, PCIe, DDR, Ethernet); ARM/RISC-V sub-systems
Define/implement IP/SoC verification plans and build verification test benches; drive verification closure using metrics and coverage
Develop functional tests, debug/root-cause failures, and ensure bug-free designs; collaborate with Design team
Collaborate across cross-functional teams (Model, Emulation, Silicon validation, full-stack) and drive continuous DV improvements and methodologies
5+ years in SystemVerilog/UVM and IP/SoC level verification
Experience with SystemVerilog Assertions, Formal or Emulation; verification infrastructure design
Proficient in EDA tools and scripting (Python/TCL/Perl/Shell); track record of first-pass success
Experience with IP/sub-system verification and high-speed interfaces
8+ years in UVM-based environments or from-scratch DV environments
IP/SoC verification for AMBA, PCIe, DDR, Ethernet; ARM/RISC-V sub-systems
Data-center workload verification (AI/ML, networking); cross-functional collaboration a
Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Track record of 'first-pass success' in ASIC (Application-Specific Integrated Circuit) development cycles 5+ years of experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification 5+ years experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Preferred Qualifications
8+ years of experience in development of UVM based verification environments from scratch Experience in IP, sub-system and SoC level verification using SystemVerilog, UVM Experience with IP or integration verification of high-speed interfaces like AMBA, PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate), Ethernet Experience with verification of ARM/RISC-V based sub-systems or SoC (Systems on Chip) Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs Experience with revision control systems like Mercurial, Git or SVN Experience working across and building relationships with cross-functional design, model and emulation teams