Full Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Summary: We are seeking a talented Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs. You will work closely with the design and development teams to create and execute comprehensive verification plans, ensuring the robustness and reliability of our products.

Key Responsibilities

• Develop and implement test plans and testbenches for verification of sub-blocks in high-speed Ethernet, UALink, PCIE PHY (64b/66b Encoder/Decoder, FEC encoder/decoder, DSP, FFE, DFE, MLSD).
• Identify, document, and debug functional issues found during verification, collaborating with design engineers for resolution.
• Develop and apply coverage models to ensure thorough validation of the design.
• Work closely with architects, designers, and software teams to comprehend the design architecture and contribute to high-level verification strategy.
• Stay up-to-date with industry best practices and emerging tools for design verification.

Qualifications

• Bachelor’s in Electrical Engineering, Computer Engineering, or a related field.
• 2+ year of experience in DV.
• Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology).
• Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim).
• Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes.
• In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols.
• Excellent analytical, debugging, and problem-solving skills.
• Strong teamwork and communication abilities.
• Pay and Benefits
• Competitive salary.
• Performance bonus each year.
• Flexible working time.
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.
• We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.