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Marvell Technology • Bucharest, Romania
Role & seniority
Stack / tools
DFT concepts, scan test, Memory Built-in Self-Test (MBIST)
Tooling: Mentor Graphics, Synopsys
HDL: Verilog/VHDL; basic scripting; Linux OS
Top 3 responsibilities
Learn and implement DFT flow for ASIC designs (insertion, synthesis, constraints, simulation)
Execute ATPG/MBIST flows and verify DFT implementations for multi-million-gate SOCs
Collaborate with global DFT team to specify and apply test technologies/methodologies
Must-have skills
Pursuing BS in Electronics, Computer Science, or related field
Basic electronics knowledge; circuits, circuit simulation
Familiarity with Verilog/VHDL
Basic programming/scripting; Linux background
Good spoken/written English
Nice-to-haves
Knowledge of defects in digital circuits
Experience with defensive debugging, automation scripts, or additional programming languages
Location & work type
Notes
Focus on learning SOC DFT implementation and ATPG/MBIST workflows using industry tools
Emphasis on collaboration within a global DFT team and exposure to advanced test methodologies
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell designs and develops ASICs for customers in critical infrastructure sectors leveraging Marvell’s leading edge IP portfolio. We are looking for a Design For Test ( DFT ) Engineer Intern to join Marvell’s Design Center in Bucharest, Romania to learn about: system-on-chip (SOC) implementation, understanding of the block level or chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex custom ASIC designs, execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST). What You Can Expect Team player in a worldwide DFT (design for test) team responsible for specification and implementation of the test technologies and methodologies for multi-million-gate ASIC designs Learning the Design-for-Test flow of ASIC design including DFT logic insertion, synthesis, constraints development, simulation, ATPG/MBIST Use state-of-the-art DFT tools by Mentor Graphics and Synopsys What We're Looking For Candidate MUST be currently pursuing a BS degree in Electronics, Computer Science or related technical field(s) 0-1 years of previous experience Basic electronics knowledge (circuits, circuit simulation, basic circuits function knowledge) Basic knowledge of Verilog/VHDL Logic gates Fair programming and scripting skills Fair Linux OS background Knowledge about defects in digital circuits is a bonus Good English (spoken and written) Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AB1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.