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Google • Sunnyvale, California, United States
Salary: $156,000 - $229,000 / year
Role & seniority: DFT Test Engineer (senior level) focused on AI/ML hardware acceleration and TPU architecture integration within Google's silicon design and verification flow.
DFT features: JTAG, MBIST, ATPG, HSIO; Scan/ATPG, SSN/Streaming Fabric; memory BIST, BISR/BIRA
Verification: SystemVerilog; pattern generation/verification; DFT integration into ASIC flow
Scripting: Python, Perl, or TCL
ATE platforms: Teradyne UltraFlex, Advantest
IP testing domains: PLL, PVT sensors, thermal diodes, PMRO, aging sensor, eFuse; PCIe, DDR, HBM
Define requirements for ATE tests and manufacturing test flow with DFT/Design teams early in design
Generate, verify, and validate ATE patterns across debug, production, HTOL/HVS/Esoe characterization; ensure high-quality pattern delivery via VTPSIM
Own pattern translations and integrate DFT verification into the ASIC design flow; prepare silicon debug strategies and test readiness for testers; participate in post-manufacturing bring-up
Bachelor's degree in ECE/CS or related field (or equivalent experience)
~8 years’ experience with DFT features (JTAG/MBIST/ATPG/HSIO), verification, and functional validation
Proficiency in SystemVerilog
Experience with one scripting language (Python, Perl, or TCL)
Experience with ATE platforms (Teradyne UltraFlex or Advantest)
*** Experience with one of the scripting languages:** Python, Perl, or TCL.
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
10 years of experience in test engineering or product engineering.
Experience with Scan/ATPG test development, especially with Streaming Scan Network (SSN)/Streaming Fabric techniques, or memory BIST test development and repair scheme implementation, including BISR/BIRA.
Experience in testing Intellectual Property (IP) such as Phase-locked Loops (PLL), Process Voltage Temperature (PVT) sensors, thermal diodes, Process Monitor Ring Oscillator (PMRO), droop detector, aging sensor, and eFuse.
Experience with PCIE, Double Data Rate (DDR) and HBM testing.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a DFT Test Engineer, you will work closely with various teams within the design process with other engineers to deliver the confidence needed in the design of the chip. You will collaborate with the Functional Verification team to develop Design for Testing (DFT) environments, drive DFT strategy, and ensure our DFT solutions are properly verified for all usage scenarios.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more
about benefits at Google [https: //careers.google.com/benefits/].
Engage with DFT and Design teams at early design stage to define requirements for ATE tests and manufacturing test flow.
Generate and verify ATE patterns, including debug level, production level, characterization, High Voltage Screen (HVS), High-Temperature Operating Life (HTOL), Electrical Stress on Environment (ESOE) etc.
Run pattern playbacks (VTPSIM) on all delivered patterns prior to silicon arrival to ensure high quality of pattern delivery.
Own pattern translations, and integrate DFT verification into the overall ASIC design flow.
Prepare silicon debug verification strategy, test plan, and readiness for testers. Participate in post-manufacturing silicon bring-up tasks.