🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Cookies & analytics consent
We serve candidates globally, so we only activate Google Tag Manager and other analytics after you opt in. This keeps us aligned with GDPR/UK DPA, ePrivacy, LGPD, and similar rules. Essential features still run without analytics cookies.
Read how we use data in our Privacy Policy and Terms of Service.
🤖 15+ AI Agents working for you. Find jobs, score and update resumes, cover letter, interview questions, missing keywords, and lots more.
Synopsys Inc • München, Brandenburg, Germany
Role & seniority: Senior/Lead ASIC Digital Design Verification expert (10+ years), hands-on leader and mentor.
Stack/tools: ASIC/UVM verification; SystemVerilog; UVM; SVA; formal verification; AI tools; C, Python, TCL/Perl; interface IPs (PCIe, CXL).
Partner with design teams to define verification requirements and develop test plans.
Build/maintain UVM testbenches and agents; review and improve test plans and code; apply SVA and formal verification; implement coverage metrics.
Lead and mentor verification engineers; drive adoption of modern verification and AI tools; reduce project risk.
10+ years in ASIC/UVM verification
Proficiency in SystemVerilog, C, Python, TCL/Perl
Experience with PCIe/CXL interfaces
Familiarity with formal verification and AI tools
B.Sc./M.Sc. in a relevant engineering field
Experience applying AI-assisted verification methods
Formal verification and advanced coverage techniques
Leadership/mentoring in a high-impact team or HPC context
Location & work type: Full-time employment; location not specified. Team is part of a high-impact HPC leadership group; work environment described as collaborative and innovative.
At Synopsys, we drive innovations that shape the world—from self-driving cars to AI and the cloud. As the global leader in chip design and verification, we empower the creation of high-performance silicon and software. Join us and transform the future through continuous technological advancement.
You’re an accomplished ASIC Digital Design Verification expert with 10+ years of experience, skilled in UVM environments and passionate about building reliable, high-performance chips. You’re a hands-on leader and mentor, eager to leverage AI tools, formal verification, and the latest methodologies. Your collaborative spirit, analytical mindset, and “can do” attitude drive your success in fast-paced, innovative environments.
Partnering with design teams to define verification requirements Developing test plans from specifications Building and maintaining UVM testbenches and agents Reviewing and improving test plans and code Applying SVA and formal verification techniques Implementing and analyzing coverage metrics Leading and mentoring verification engineers
Accelerate silicon development and time-to-market Ensure robust, high-quality chip verification Drive adoption of modern verification and AI tools Reduce project risks through thorough coverage Deliver complex IP for next-gen technologies Mentor and grow technical teams
B. Sc./M.Sc. in a relevant engineering field
Analytical and innovative Collaborative communicator Positive, adaptable leader and mentor
Join a high-impact HPC leadership team delivering complex IPs, leading engineers across multiple product verticals in a collaborative, innovative environment.
We offer a comprehensive range of health, wellness, and financial benefits. Details on salary and benefits will be provided during the hiring process.
Karrierestufe Management Beschäftigungsverhältnis Vollzeit Tätigkeitsbereich Design, Unternehmensberatung und Ingenieurwesen Branchen Herstellung von Halbleitern, Softwareentwicklung und Herstellung von Computerhardware