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Astera Labs • Israel
Role & seniority: Design Verification Manager; senior/leadership level (15+ years ASIC verification; 5+ years in technical leadership)
Stack/tools: ASIC verification (unit, sub-system, SoC); SV-UVM, Formal, Emulation; DV architecture; Python/Tcl automation; high-speed protocols (AMBA, PCIe, Ethernet, CXL)
Lead and mentor the verification team; define technical roadmap and methodology for ASIC verification
Drive comprehensive verification plans and ensure functional requirements are met on schedule across units and full-chip levels
Oversee multiple verification strategies (DV with SV-UVM, Formal, Emulation); define functional coverage goals and drive 100% verification closure; align with Design/Architecture/Backend on specs and root-causes
B.Sc. in Electrical Engineering or related field
15+ years of ASIC verification experience; 5+ years in technical leadership or people management
Deep, hands-on expertise in building verification environments for IPs, blocks, and full-chip designs
Expert-level knowledge of verification methodologies; project and resource management; strong stakeholder influence
Experience with SV-UVM for complex systems; Formal Verification or Emulation at team level
Python/Tcl automation for verification workflows
Deep understanding of high-speed protocols (AMBA, PCIe, Ethernet, CXL)
Location & work type: Israel-based strategic R&D center (on-si
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve critical 'data bottlenecks' enabling the future of AI at scale. This is a unique opportunity to take on meaningful product ownership in a new site and help build our local engineering powerhouse from the ground up. We are seeking a visionary Design Verification Manager to lead the quality and reliability strategy for our Israel R&D center. If you thrive on solving complex, uncWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.harted challenges in deep-submicron processes, this role is for you. About the role As a Design Verification Manager, you will be responsible for steering the verification roadmap, overseeing the development of complex testbenches, and ensuring our next-generation AI silicon meets the highest standards of excellence. Leading a team of talented engineers, you will tackle challenges at the unit, sub-system, and full-chip levels, playing a pivotal leadership role in delivering high-performance hardware for the world's largest AI clusters.
B. Sc. in Electrical Engineering from a leading academic institution