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Cadence Design Systems • San Jose, California, United States
Salary: 100 Best Compa
Role & seniority: Lead Mixed-Signal Verification Engineer (senior individual contributor/lead)
Stack/tools: Mixed-signal DV; Cadence tools (Virtuoso/ADE, Xcelium); AMS flows; Verification infra (test-benches, environments, scripting); IPG context (SerDes, DDR, A2D converters); languages: C++, Python, SystemVerilog; e; UVM; revision control basics
Define and drive metric-driven mixed-signal verification plans, models, roadmaps, and complete DV solutions across digital/analog/AMS domains
Architect and implement scalable mixed-signal verification flows, VIP integration, emulation, power/CPF-UPF integration, and debug solutions; mentor junior engineers
Collaborate with Digital, Analog, Firmware, Test teams and internal tools groups to push efficient, accurate mixed-signal methodologies and ensure coverage across IPG offerings
4+ years in Digital and Analog mixed-signal environments
Experience creating verification infrastructure (test-benches, environments, scripting); flow scripting and design automation; debugging verification test cases
Knowledge of standards (PCIe, USB, DDR4) and ability to communicate cross-functionally
Familiarity with SystemVerilog/UVM, mixed-signal Cadence tools, and basic revision control
Proficiency in multiple programming languages (C++, Python, SystemVerilog, e)
Deep knowledge of mixed-signal methodology and AMS simulation flows
Experience wit
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Lead Mixed-Signal Verification Engineer is responsible for defining mixed-signal verification plans, models, and roadmaps and delivering complete Mixed-Signal DV solutions that address challenges across the full spectrum of diverse mixed-signal products. This also includes driving innovation across the Mixed-Signal verification flow to create efficient and accurate mixed-signal methodologies. The ideal candidate is expected to be a mixed-signal DV expert and the hub between all engineering teams. Duties: Architect, develop, champion, and implement metric-driven mixed-signal verification solutions, in the areas of: Digital/DMS/AMS testbench creation and generation Automatic Model generation and testing Cadence Design Systems AMS simulation flows Mixed-Signal Assertions and Checkers Behavioral Modeling and Model Validation Methodologies Mixed-Signal VIP integration and testing Mixed-Signal emulation flows and practices Power intent verification including Low power states, state retention, and CPF/UPF integration Push technology for mixed-signal modeling, simulation, and DV in order to improve mixed-signal verification efficiency and accuracy. Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters, and custom solutions Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification Develop efficient debug solutions and techniques Develop an efficient and accurate full-stack mixed-signal methodology for the entire IP stack from the controller to the analog circuit. Propagate mixed-signal knowledge and mentor junior engineers Collaborate closely with: Digital, Analog, Firmware, and Test engineers Internal methodology and tool development teams, such as Virtuoso/ADE/Xcelium. PDK teams Customer management and engineering support teams Qualifications 4+ Years’ experience in working with Digital and Analog mixed-signal environments and teams. Must have good written and verbal cross-functional communication skills. Proven experience in most of the following: Creating Verification infrastructure (test-bench, environment, scripting) Scripting of verification flows, design automation Debugging verification test cases Knowledge of existing and upcoming standards such as PCIE, USB, DDR4, etc. Must be comfortable interacting across the IPG development team including the ability to understand design constraints. Knowledge of multiple programming languages. C++, Python, System Verilog, and e (verification language) are a plus Knowledge of Mixed-Signal Cadence tools and mixed-signal methodology is a plus Knowledge of System Verilog and UVM Test environment and methods is a plus Working knowledge of revision control tools such as SOS, SVN is a plus Education Level: Bachelor's Degree (MSEE/PhD Preferred) #LI-MA1 We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact . Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.