Role & seniority: Formal Verification Engineer (focus on sign-off for complex RTL; role appears mid-to-senior level based on responsibilities)

Stack/tools

Formal Verification methodologies and sign-off processes
SystemVerilog Assertions (SVA) or PSL
Metrics-Driven Verification (test planning & coverage)
Scripting: Python, Perl, or TCL
Cadence JasperGold, VManager (desirable)
Collaboration with RTL/design teams (micro-architecture specifications)

Top 3 responsibilities

Develop and implement formal verification methodologies and best practices for design sign-off; prepare verification plans based on specifications
Document results, coverage metrics, and manage project plans; maintain formal verification environment
Create reusable formal models/verification codebases; participate in RTL design reviews and track/close design bugs

Must-have skills

Proven track record verifying complex ASIC/FPGA designs (preferably high-volume)
Deep Formal Verification expertise, with experience using SVA or PSL
Metrics-Driven Verification skills (planning and coverage closure)
Strong knowledge of ISA, interrupt handling, and bus architectures
Scripting for automation (Python, Perl, or TCL)

Nice-to-haves

Experience with Cadence JasperGold and VManager
SerDes/high-speed signaling domain experience
Formal verification for sign-off in mixed-signal or high-speed interconnect contexts

Location & work type

Laus

Full Description

Mixed Signal Verification Engineer - SerDes / High Speed

We are partnered with a specialist semiconductor company delivering complex high-speed signaling and interconnect solutions. They are seeking a Formal Verification Engineer to establish and implement formal methodologies for sign-off on advanced RTL designs.

This is a permanent position based in Lausanne, Switzerland (it is also possible to work from offices in the UK, Germany, or Denmark).

Key Responsibilities for this Formal Verification Engineer position

Develop and implement Formal Verification (FV) methodologies and best practices for design sign-off.
Prepare comprehensive design verification plans based on design specifications.
Document results and coverage metrics for formal sign-off.
Plan and schedule assigned projects and maintain the formal verification environment.
Work with RTL design engineers to develop formal micro-architecture specifications.
Deliver reusable and optimized formal models and verification codebases to improve efficiency.
Participate in RTL design reviews and actively track and close design bugs.

Key Requirements

Proven track record in verifying complex ASIC or FPGA designs (preferably in high-volume applications).
Deep understanding of Formal Verification technologies.
Proficiency in temporal logic assertion-based languages such as SystemVerilog Assertions (SVA) or PSL.
Strong knowledge of Metrics-Driven Verification (test planning and coverage closure).
Strong understanding of instruction-set architectures, interrupt handling, and bus architectures.
Proficiency in scripting for automation (Python, Perl, or TCL).
Experience with Cadence JasperGold and VManager is desirable.

Keywords: Formal Verification Engineer / Formal Verification / FV / SVA / PSL / Assertion-Based Verification / Metrics-Driven Verification / RTL Design / JasperGold / VManager / ASIC / FPGA / Verification Methodology / Semiconductor / SerDes / Scripting

If you are interested in this Formal Verification Engineer position, please send a copy of your CV to ts@eu-recruit.com

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Formal Verification Engineer - Advanced RTL