Role & seniority: Formal Verification Engineer (mid-senior level; 5+ years in semiconductor)

Stack/tools: Formal verification technologies; SVA/PSL; Python/Perl/TCL for automation; regression setup & management; design verification planning; RTL collaboration; coverage metrics; bug tracking

Top 3 responsibilities

Develop formal verification methodologies and best practices; contribute to RTL design reviews
Prepare design verification plan based on specifications; document results and coverage for formal sign-off
Plan and schedule projects; maintain verification environment; track and close design bugs

Must-have skills

5+ years in semiconductor, proven verification of complex FPGA/ASIC designs
Ability to balance quality vs. schedule; regression and automation scripting (Python/Perl/TCL)
Deep understanding of Formal Verification, metrics-driven verification, and SVA/PSL
Experience collaborating with RTL engineers to derive formal micro-architectures

Nice-to-haves

Familiarity with SerDes and high-level protocols (PCIe, USB, DP)
Knowledge of traditional simulation-based verification
Delivered reusable formal models/verification codebases
Location & work type: Lausanne (Switzerland) or Reading/Northampton (UK) or Dortmund (Germany) offices; on-site or hybrid arrangement likely; full-time role.

Full Description

Formal Verification Engineer

European Tech Recruit are working closely with a leading semiconductor company, based in Lausanne, who are looking for a talented Formal Verification Engineer to join their team.

This role can also be available working out of their Reading (UK), Northampton (UK) or Dortmund (Germany) offices.

Responsibilities as Formal Verification Engineer

Develop formal verification methodologies and best practices.
Participate in RTL design reviews.
Prepare design verification plan based on design specifications.
Document results and coverage metrics for formal sign-off.
Plan and schedule assigned projects for timely completion.
Maintain design verification environment and track & close design bugs.

Requirements

5+ years’ experience in the semiconductor industry.
Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC.
Skilled in trade-offs between quality and schedule.
Good scripting techniques (python, Perl or TCL for automation), regression setup & management.
Deep understanding of Formal Verification technologies.
Strong knowledge on Metrics-driven verification (incl. test planning and coverage closure).
Proficiency in temporal logic assertion-based languages such as SVA or PSL.
Knowledge of traditional simulation-based verification methodologies (a plus).
Working with RTL design engineers to develop a formal micro-architecture specification.
Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous.
Delivered reusable and optimized formal models and verification codebases to improve efficiency across project.

If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to nh@eu-recruit.com.

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