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Efficient Computer • San Jose, California, United States
Salary: $210,000 - $250,000 / year
Role & seniority: Design Verification & Emulation Manager (senior/lead level) within HW engineering; people leadership responsibility for verification and emulation teams.
Stack/tools: UVM-based verification; constrained-random, coverage-driven closure, assertions (SVA), formal verification; SystemVerilog/Verilog; C/C++; Python, Tcl; emulation platforms (Palladium, ZeBu, Veloce); FPGA prototyping flows; hybrid simulation-emulation; AI/ML-assisted verification techniques; power-aware verification (UPF/CPF); DV flow automation.
Define end-to-end verification strategy from block-level to full-chip, including emulation-based validation and prototyping.
Own UVM methodology, coverage, assertions, formal techniques, and drive cross-environment sign-off; lead debug and root-cause analysis across simulation and emulation.
Build, mentor, and scale a verification/emulation team; manage schedules, risk, and vendor/lab infrastructure; align verification with tapeout readiness and cross-functional partners.
12+ years in ASIC/SoC verification; 3–5+ years in management/senior technical leadership overseeing verification and emulation.
Deep expertise in UVM, constrained-random, functional coverage, assertions, and formal verification; strong debug skills.
Hands-on with at least one major emulation platform (Palladium, ZeBu, Veloce) and FPGA prototyping; SystemVerilog/Verilog; C/C++; scripting (Python, Tcl).
SoC a
Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution Efficient is looking for a seasoned Design Verification & Emulation Manager to staff, lead and scale our verification and emulation organization which is part of our newly formed HW engineering organization. This is a high-impact leadership role responsible for ensuring silicon correctness and system-level readiness across multiple industry defining product lines. You will own the verification strategy from block-level to full-chip, drive emulation-based validation for early software enablement, and build a world-class team of verification and emulation engineers. This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond! Key Responsibilities Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising Deliver pre-silicon platforms for early software development in partnership with firmware and software teams Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership Build, mentor, and scale a high-performing team of verification and emulation engineers Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness Represent verification and emulation in tapeout readiness reviews and program-level decision forums Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques. Define right DV mix for in-house vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals. Required Qualifications & Experience
Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain). Preferred Qualification Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation. Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges. Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization). We offer a competitive salary for this role, generally ranging from $210,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate. Why Join Efficient? Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.