Full Description

Position Overview We are seeking a hands-on ASIC Design Verification Lead to own verification execution for complex, high-performance networking silicon. This role is a senior technical leadership position focused on driving verification strategy, infrastructure, and closure, while remaining deeply involved in day-to-day hands-on verification work. This is not a people-manager-only role. The ideal candidate is a highly technical verification leader who has personally taken chips to tape-out, understands how verification breaks late in the cycle, and can drive functional correctness, coverage closure, and tape-out readiness in a fast-moving startup environment. Responsibilities Verification Strategy & Execution Define and own block-, subsystem-, and chip-level verification strategies Develop and maintain scalable verification environments using SystemVerilog and UVM Drive execution from test-plan definition through coverage and bug closure Ensure verification readiness as a gating requirement for tape-out Hands-on Verification Development Write and review high-quality testbenches, sequences, checkers, and scoreboards Develop constrained-random, directed, and stress tests to validate complex corner cases Actively debug functional failures across RTL, testbench, and simulation environments Coverage & Quality Ownership Define functional, code, and assertion coverage goals Analyze coverage results and identify verification gaps Provide clear, actionable feedback to RTL designers to improve design and test quality Cross-Functional Debug & Collaboration Partner closely with RTL, architecture, physical design, and firmware teams Drive root-cause analysis of functional, performance, and integration issues Support gate-level, timing-aware, and power-aware simulations as required Partner and support emulation and post silicon validation of the ASIC design Full-Chip & Pre-Silicon Validation Lead full-chip verification planning, execution, and closure Support emulation and acceleration environments where appropriate Ensure clean handoff to silicon bring-up teams with high confidence in design correctness Execution Discipline & Technical Leadership Establish and enforce verification checklists and quality gates Track verification progress and risk, proactively escalating issues Lead by technical authority and hands-on contribution rather than coordination alone Continuously improve verification methodology, infrastructure, and best practices Qualifications Strong hands-on experience in ASIC design verification Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership Deep expertise in SystemVerilog and UVM-based verification methodologies Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug Experience with block-level through full-chip verification and integration Ability to drive execution in ambiguous, fast-paced startup environments Excellent communication skills and ability to collaborate across disciplines Nice to Have Networking ASIC verification experience (Ethernet-based systems preferred) Experience with gate-level, timing-aware, and low-power verification Familiarity with high-speed interfaces and chip-to-chip interconnects Experience with emulation, acceleration, or FPGA-based validation Post-silicon debug experience and RTL-to-silicon correlation

Why Join Us? At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.